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	<title>Edge AI Archives - Tauro Technologies</title>
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		<title>Holoscan Platform for Robotics and Edge AI</title>
		<link>https://taurotech.com/blog/holoscan-platform-for-robotics-and-edge-ai/?utm_source=rss&#038;utm_medium=rss&#038;utm_campaign=holoscan-platform-for-robotics-and-edge-ai</link>
		
		<dc:creator><![CDATA[Anna Badalyan]]></dc:creator>
		<pubDate>Sun, 09 Nov 2025 00:07:39 +0000</pubDate>
				<category><![CDATA[Embedded Systems]]></category>
		<category><![CDATA[Hardware design]]></category>
		<category><![CDATA[Robotics]]></category>
		<category><![CDATA[Defense AI Hardware]]></category>
		<category><![CDATA[Edge AI]]></category>
		<category><![CDATA[Edge Computing]]></category>
		<category><![CDATA[Ethernet Camera Systems]]></category>
		<category><![CDATA[GPU Direct RDMA]]></category>
		<category><![CDATA[MIPI-CSI]]></category>
		<category><![CDATA[NVIDIA Holoscan]]></category>
		<category><![CDATA[Real-Time Embedded Systems]]></category>
		<category><![CDATA[Robotics Vision]]></category>
		<category><![CDATA[Sensor Fusion]]></category>
		<guid isPermaLink="false">https://taurotech.com/?p=3846</guid>

					<description><![CDATA[<p>Holoscan Platform for Robotics and Edge AI   Ethernet Sensor Bridges and the Next Generation of Edge AI Systems For more than a decade, embedded vision systems have relied on two dominant interfaces: MIPI-CSI and GMSL. These standards were good enough for automotive ADAS, drones, and early robotics. They offered reliability and adequate bandwidth at&#8230;</p>
<p>The post <a href="https://taurotech.com/blog/holoscan-platform-for-robotics-and-edge-ai/">Holoscan Platform for Robotics and Edge AI</a> appeared first on <a href="https://taurotech.com">Tauro Technologies</a>.</p>
]]></description>
										<content:encoded><![CDATA[


<h1 class="wp-block-heading" style="text-align: center;">Holoscan Platform for Robotics and Edge AI</h1>



<h2 class="wp-block-heading"> </h2>
<h2 style="text-align: left;"><strong>Ethernet Sensor Bridges and the Next Generation of Edge AI Systems</strong></h2>



<p class="wp-block-paragraph">For more than a decade, embedded vision systems have relied on two dominant interfaces: MIPI-CSI and GMSL. These standards were good enough for automotive ADAS, drones, and early robotics. They offered reliability and adequate bandwidth at a small scale.</p>



<p class="wp-block-paragraph">But the requirements have changed:</p>



<ul class="wp-block-list">
<li>Defense programs&nbsp;now field distributed sensor fusion across vehicles, ships, and unmanned systems.</li>



<li>Robotics&nbsp;are moving from lab prototypes with two or three cameras to fleets with dozens of vision, radar, and lidar nodes.</li>



<li>Healthcare and industrial inspection&nbsp;demand higher bandwidth, tighter synchronization, and safety-certifiable architectures.</li>
</ul>



<p class="wp-block-paragraph">In this environment, MIPI and GMSL show their limits.</p>



<h3 class="wp-block-heading"><strong>Why It’s Time to Move Beyond MIPI-CSI and GMSL</strong></h3>



<h3 class="wp-block-heading">MIPI-CSI:</h3>



<ul class="wp-block-list">
<li>Short&nbsp;reach &#8211; designed for PCB-level connections, not vehicle&nbsp;or platform-scale systems.&nbsp;The cable length is limited to around 30cm.</li>



<li>Point-to-point only &#8211; every new sensor requires a direct link, adding complexity as counts grow.</li>



<li>Scaling beyond a few links requires custom bridges or FPGAs.</li>
</ul>



<h3 class="wp-block-heading">GMSL:</h3>



<ul class="wp-block-list">
<li>Built for automotive, with EMI resilience and reliable coax transmission.</li>



<li>Practical for 2–6 cameras, but scaling further is complex.</li>



<li>Proprietary PHYs lock you to vendors.</li>



<li>No multicast&nbsp;support: every stream is point-to-point.</li>



<li>Synchronization limited by PHY-level timing, not system-wide clocks.</li>
</ul>



<p class="wp-block-paragraph">Shared flaw: both push sensor data through the CPU&nbsp;before the GPU. That means extra latency, jitter from OS scheduling, and additional CPU heat&nbsp;&#8211; already the thermal bottleneck in many rugged systems.</p>



<p class="wp-block-paragraph">For defense and robotics, these constraints can be showstoppers.</p>



<h3 class="wp-block-heading"><strong>Ethernet + Holoscan Changes the Model</strong></h3>



<p class="wp-block-paragraph">NVIDIA’s Holoscan SDK and Thor AGX platform shift sensor ingress from CPU-managed links to Ethernet with GPUDirect RDMA. This architecture streams data directly into GPU memory, bypassing the CPU entirely.</p>


<div class="wp-block-image">
<figure class="aligncenter size-full is-resized"><img fetchpriority="high" decoding="async" width="1403" height="385" src="https://taurotech.com/wp-content/uploads/2025/10/Picture1-1.png" alt="Architecture diagram of Holoscan Sensor Bridge showing the Tauro Technologies DA322 connecting various sensors via MIPI D-PHY to an NVIDIA Jetson Thor platform through an Ethernet connection." class="wp-image-3857" style="aspect-ratio:3.64429022643356;width:982px;height:auto" srcset="https://taurotech.com/wp-content/uploads/2025/10/Picture1-1.png 1403w, https://taurotech.com/wp-content/uploads/2025/10/Picture1-1-768x211.png 768w" sizes="(max-width: 1403px) 100vw, 1403px" /><figcaption class="wp-element-caption">Figure 1:&nbsp;Holoscan Sensor Bridge Architecture</figcaption></figure>
</div>


<h3 class="wp-block-heading">Engineering implications:</h3>



<ul class="wp-block-list">
<li><strong><em>Lower </em></strong><strong><em>Latency</em></strong><br>Removing CPU buffering eliminates context switches and driver overhead. Benchmarks show up to <em>5× lower latency compared to USB, and ~1.5× lower compared to MIPI</em>. For radar, EO/IR, or autonomy pipelines where microseconds matter, this is decisive.</li>



<li><strong><em>Determinism</em></strong><strong><em><br></em></strong>With no OS scheduling in the path, jitter drops significantly. IEEE 1588-2019 PTP synchronization aligns multiple boards to sub-microsecond precision. Distributed arrays of sensors can now operate in phase across vehicles or unmanned platforms.</li>



<li><strong><em>Thermal headroom</em></strong><strong><em><br></em></strong>CPUs no longer manage sensor ingress. That frees cycles, reduces utilization, and most importantly, cuts heat generation. In rugged defense and robotics deployments, where cooling is the hardest part of the design, this translates directly into more reliable systems.</li>



<li><strong><em>Scalability<br></em></strong>Adding sensors means adding Ethernet bandwidth or switch ports. The same network that supports four cameras today can support forty tomorrow &#8211; without redesigning CPU pipelines.</li>



<li><strong><em>Multicast<br></em></strong>A single camera feed can be consumed by multiple GPU pipelines simultaneously &#8211; one for navigation, one for targeting, one for operator display. GMSL and MIPI topologies can’t do this natively.</li>



<li><strong><em>Safety and Security</em></strong><strong><em><br></em></strong>Ethernet brings built-in support for MACSec, packet watermarking, redundancy, and hooks for SIL-2 compliance. These features are not bolt-ons but part of the end-to-end architecture.</li>
</ul>



<p class="wp-block-paragraph">This is not just a faster pipeline. It is a cleaner, more efficient system design for multi-sensor AI workloads.</p>



<h3 class="wp-block-heading"><strong>What is </strong><strong>NVIDIA </strong><strong>Holoscan</strong><strong>?</strong></h3>



<p class="wp-block-paragraph">Holoscan is a multimodal computing platform designed for the edge, providing an accelerated end-to-end software stack for scalable, software-defined, real-time processing of streaming data.</p>



<h3 class="wp-block-heading"><strong>Holoscan Sensor Bridge Software</strong></h3>



<p class="wp-block-paragraph">&nbsp;&nbsp;Holoscan Sensor Bridge software&nbsp;consists of two main components:</p>



<ul class="wp-block-list">
<li>NVIDIA Holoscan SDK&nbsp;– Build high-performance streaming applications by composing modular operators into customizable pipelines</li>



<li>Holoscan Sensor Bridge host software &#8211; Build custom pipelines and process data from network-connected sensors using ready-to-use operators for tasks such as image conversion, signal processing, inference, and visualization</li>
</ul>



<p class="wp-block-paragraph">Holoscan applications&nbsp;separate the main application and define the data pipeline with the necessary operators in a configure method.</p>


<div class="wp-block-image">
<figure class="aligncenter size-full is-resized"><a href="https://docs.nvidia.com/jetson/archives/r38.2.1/DeveloperGuide/SD/CameraDevelopment/CoECameraDevelopment/SIPL-for-L4T/CoE-Solution-Overview.html"><img decoding="async" width="1389" height="381" src="https://taurotech.com/wp-content/uploads/2025/10/Picture2-1.png" alt=" Holoscan Sensor Bridge Pipeline on Jetson AGX Thor Platform with Hardware ISP" class="wp-image-3858" style="aspect-ratio:3.645816714372859;width:1106px;height:auto" srcset="https://taurotech.com/wp-content/uploads/2025/10/Picture2-1.png 1389w, https://taurotech.com/wp-content/uploads/2025/10/Picture2-1-768x211.png 768w" sizes="(max-width: 1389px) 100vw, 1389px" /></a><figcaption class="wp-element-caption"><a href="https://docs.nvidia.com/jetson/archives/r38.2.1/DeveloperGuide/SD/CameraDevelopment/CoECameraDevelopment/SIPL-for-L4T/CoE-Solution-Overview.html">Figure 2:&nbsp;Holoscan Sensor Bridge Pipeline on Jetson AGX Thor Platform with Hardware ISP</a></figcaption></figure>
</div>


<p class="wp-block-paragraph">With the User Space API, HSB connects sensor operation with the Linux endpoint in a way that developers focus on the pipeline and the operations required for the specific application.</p>


<div class="wp-block-image">
<figure class="aligncenter size-full is-resized"><img decoding="async" width="1374" height="1005" src="https://taurotech.com/wp-content/uploads/2025/10/Picture3-1.png" alt="Software stack diagram for the Holoscan Sensor Bridge, illustrating layers from the Linux kernel and Transport Abstraction Layer up through Holoscan (User Space API), sensor drivers, and the final end application." class="wp-image-3859" style="aspect-ratio:1.3671790250171065;width:803px;height:auto" srcset="https://taurotech.com/wp-content/uploads/2025/10/Picture3-1.png 1374w, https://taurotech.com/wp-content/uploads/2025/10/Picture3-1-768x562.png 768w" sizes="(max-width: 1374px) 100vw, 1374px" /><figcaption class="wp-element-caption">Figure 3:&nbsp;Holoscan Sensor Bridge Software</figcaption></figure>
</div>


<h3 class="wp-block-heading"><strong>Holoscan Sensor Bridge </strong><strong>Performance</strong></h3>



<p class="wp-block-paragraph">Embedded systems require high-resolution, high-frame-rate data with low latency and precise synchronization. <a href="https://taurotech.com/products/nvidia-holoscan/">Holoscan Sensor Bridge (HSB)</a> meets these requirements, delivering up to 5&nbsp;times&nbsp;lower latency than USB cameras&nbsp;(119ms)&nbsp;and 1.5&nbsp;times&nbsp;lower latency than MIPI cameras&nbsp;(37ms). By leveraging RDMA and camera&nbsp;over&nbsp;Ethernet, HSB transfers data directly into GPU memory with virtually zero CPU utilization, enabling real-time processing and faster system response.</p>


<div class="wp-block-image">
<figure class="aligncenter size-full is-resized"><a href="https://developer.nvidia.com/blog/nvidia-holoscan-sensor-bridge-empowers-developers-with-real-time-data-processing/"><img loading="lazy" decoding="async" width="1383" height="535" src="https://taurotech.com/wp-content/uploads/2025/10/Picture4-2.png" alt="Performance benchmark bar chart comparing latency between a USB Camera (119 ms) and MIPI Camera (37 ms) on AGX Orin versus the Holoscan Sensor Bridge (HSB) Camera on AGX Orin (17 ms) and AGX Thor (Target), highlighting a 5X performance improvement." class="wp-image-3862" style="aspect-ratio:2.585124175581432;width:952px;height:auto" srcset="https://taurotech.com/wp-content/uploads/2025/10/Picture4-2.png 1383w, https://taurotech.com/wp-content/uploads/2025/10/Picture4-2-768x297.png 768w" sizes="(max-width: 1383px) 100vw, 1383px" /></a><figcaption class="wp-element-caption"><a href="https://developer.nvidia.com/blog/nvidia-holoscan-sensor-bridge-empowers-developers-with-real-time-data-processing/">Figure 4:&nbsp;Holoscan Sensor Bridge Performance Benchmark Compared to Alternatives</a></figcaption></figure>
</div>


<p class="wp-block-paragraph">HSB&nbsp;enhances embedded system performance by replacing traditional kernel-space camera drivers with user-space APIs, eliminating the need for separate drivers for camera and control functionalities. This approach simplifies development complexity, allowing developers to focus on application logic. HSB&#8217;s modular design supports various Image Signal Processor (ISP) options, including NVIDIA CUDA-based ISPs, soft-ISP implementations on HSB hardware, and internal ISPs found on NVIDIA Jetson AGX and IGX platforms.</p>



<h3 class="wp-block-heading"><strong>Precision Time Protocol (PTP)</strong></h3>



<p class="wp-block-paragraph">One of the key features supported by HSB is Precision Time Protocol (PTP), which enables the HSB to synchronise its internal clock with the host system. HSB achieves&nbsp;synchronisation accuracy of 1µs and better, allowing&nbsp;developers to precisely&nbsp;track exactly&nbsp;when each event occurs&nbsp;and align data across multiple sources.</p>


<div class="wp-block-image">
<figure class="aligncenter size-full is-resized"><img loading="lazy" decoding="async" width="1378" height="645" src="https://taurotech.com/wp-content/uploads/2025/10/Picture5-1.png" alt="Multi-sensor synchronization diagram for Holoscan Sensor Bridge (HSB) illustrating the hardware clock alignment between an FPGA, a camera, and a host system using PTP, timestamped packets, and VSYNC generation for precise data capture." class="wp-image-3863" style="aspect-ratio:2.136448988107657;width:874px;height:auto" srcset="https://taurotech.com/wp-content/uploads/2025/10/Picture5-1.png 1378w, https://taurotech.com/wp-content/uploads/2025/10/Picture5-1-768x359.png 768w" sizes="(max-width: 1378px) 100vw, 1378px" /><figcaption class="wp-element-caption">Figure 5: HSB Multi-Sensor Synchronisation Diagram</figcaption></figure>
</div>


<h3 class="wp-block-heading"><strong>Sensor Bridges</strong><strong>: </strong><strong>Why They Matter</strong></h3>



<p class="wp-block-paragraph">Holoscan defines the architecture, but engineers still need a way to connect physical sensors to an Ethernet network. This is where sensor bridges come in.</p>



<ul class="wp-block-list">
<li>NVIDIA provides the GPUs and SDK.</li>



<li>Lattice offers a Holoscan devkit &#8211; useful for exploration, but built around dual FPGAs and not production-ready.</li>



<li>What the market lacks is a deployable bridge: something engineers can prototype with in the lab, then bolt directly into a rugged system without redesign.</li>
</ul>



<p class="wp-block-paragraph">That gap is exactly what Tauro Technologies’ DA322 Holoscan MIPI Adapter fills.</p>



<h3 class="wp-block-heading"><strong>DA322 Holoscan MIPI Adapter</strong></h3>



<p class="wp-block-paragraph">The DA322 provides a compact, rugged bridge from MIPI sensors into an Ethernet-based Holoscan pipeline</p>



<li>10GbE SFP+ output.</li>



<li>CertusPro-NX FPGA for deterministic bridging.</li>



<li>IEEE 1588 PTP support for sub-microsecond synchronization.</li>



<li>Compact 75×45×15mm form factor, 4.5–17 VDC input, low power.</li>


<div class="wp-block-image">
<figure class="aligncenter size-large is-resized"><img loading="lazy" decoding="async" width="929" height="574" src="https://taurotech.com/wp-content/uploads/2025/11/New-DA322-edited-1.png" alt="Tauro Technologies DA322 Holoscan MIPI Adapter" class="wp-image-4170" style="aspect-ratio:1.6185095507129406;width:440px;height:auto" srcset="https://taurotech.com/wp-content/uploads/2025/11/New-DA322-edited-1.png 929w, https://taurotech.com/wp-content/uploads/2025/11/New-DA322-edited-1-768x475.png 768w" sizes="(max-width: 929px) 100vw, 929px" /><figcaption class="wp-element-caption"><a href="https://taurotech.com/products/nvidia-holoscan/da322-holoscan/">Figure 6: DA322 Holoscan MIPI Adapter</a></figcaption></figure>
</div>

<p><!-- /wp:post-content --><!-- wp:paragraph --></p>
<p>Unlike devkits, the DA322 is production-ready. It supports two distinct use cases:</p>
<p><!-- /wp:paragraph --><!-- wp:list {"ordered":true} --></p>
<ol>
<li style="list-style-type: none;">
<ol><!-- wp:list-item -->
<li><em><strong>Prototyping</strong>:</em> Engineers can connect up to four MIPI sensors, stream over 10GbE, and validate Holoscan pipelines quickly.</li>
</ol>
</li>
</ol>
<p><!-- /wp:list-item --><!-- wp:list-item --></p>
<ol>
<li style="list-style-type: none;">
<ol>
<li><em><strong>Deployment</strong>: </em>The same hardware can be mounted in defense platforms, robotic fleets, or medical devices without a redesign. The DA322 is only 75×45×15mm and can be sized down/up depending on product requirements.</li>
</ol>
</li>
</ol>
<p><!-- /wp:list-item --></p>
<p><!-- /wp:list --><!-- wp:heading --></p>
<h3><strong>Roadmap: Beyond 4-Lane MIPI</strong></h3>
<p><!-- /wp:heading --><!-- wp:paragraph --></p>
<p>The DA322 demonstrates the model with four MIPI CSI-2 D-PHY lanes. However, some real-world systems require a mix of sensor types and counts. Tauro Technologies has deployed customized systems with I/O, including:</p>
<p><!-- /wp:paragraph --><!-- wp:list --></p>
<ul>
<li style="list-style-type: none;">
<ul><!-- wp:list-item -->
<li><em><strong>GMSL bridges:</strong> </em> to migrate automotive-grade sensors into Ethernet topologies without redesign.</li>
</ul>
</li>
</ul>
<p><!-- /wp:list-item --><!-- wp:list-item --></p>
<ul>
<li style="list-style-type: none;">
<ul>
<li><em><strong>Radar/Lidar bridges</strong>:</em>  extending the same low-latency Ethernet path to RF and optical sensing modalities.</li>
</ul>
</li>
</ul>
<p><!-- /wp:list-item --><!-- wp:list-item --></p>
<ul>
<li style="list-style-type: none;">
<ul>
<li><em><strong>Custom I/O variants:</strong></em>  bespoke designs with the right mix of ingress interfaces for primes and OEMs.</li>
</ul>
</li>
</ul>
<p><!-- /wp:list-item --></p>
<p><!-- /wp:list --><!-- wp:paragraph --></p>
<p>Product design and flexibility are Tauro Technologies’ specialty &#8211; sensor ingress tailored to your exact requirements.</p>
<p><!-- /wp:paragraph --><!-- wp:heading --></p>
<h3><strong>Why It Matters for Your Next System</strong></h3>
<p><!-- /wp:heading --><!-- wp:paragraph --></p>
<p>For engineers building the next generation of edge AI systems, the benefits are clear:</p>
<p><!-- /wp:paragraph --><!-- wp:list --></p>
<ul>
<li style="list-style-type: none;">
<ul><!-- wp:list-item -->
<li><em><strong>Remove the CPU bottleneck</strong>:</em> Lower latency, lower jitter, and reduced thermal load.</li>
</ul>
</li>
</ul>
<p><!-- /wp:list-item --><!-- wp:list-item --></p>
<ul>
<li style="list-style-type: none;">
<ul>
<li><em><strong>Scale without rework</strong>:</em> Ethernet networks scale naturally as sensor counts grow.</li>
</ul>
</li>
</ul>
<p><!-- /wp:list-item --><!-- wp:list-item --></p>
<ul>
<li style="list-style-type: none;">
<ul>
<li><em><strong>Meet determinism and safety requirements</strong>:</em> PTP sync, SIL-2 compliance, built-in security.</li>
</ul>
</li>
</ul>
<p><!-- /wp:list-item --><!-- wp:list-item --></p>
<ul>
<li style="list-style-type: none;">
<ul>
<li><em><strong>Prototype and deploy on the same hardware</strong>:</em> Faster development cycles and lower NRE.</li>
</ul>
</li>
</ul>
<p><!-- /wp:list-item --></p>
<p><!-- /wp:list --><!-- wp:paragraph --></p>
<p>GMSL and MIPI fit the previous generation. Ethernet + Holoscan is right for the next one.</p>
<p><!-- /wp:paragraph --><!-- wp:heading --></p>
<h3><strong>Conclusion</strong></h3>
<p><!-- /wp:heading --><!-- wp:paragraph --></p>
<p>Every major industry that outgrew point-to-point links &#8211; from datacenters to telecom to automotive &#8211; standardized on Ethernet. Sensor fusion for AI is following the same trajectory.</p>
<p><!-- /wp:paragraph --><!-- wp:list --></p>
<ul>
<li style="list-style-type: none;">
<ul><!-- wp:list-item -->
<li>MIPI-CSI: good for phones and embedded modules.</li>
</ul>
</li>
</ul>
<p><!-- /wp:list-item --><!-- wp:list-item --></p>
<ul>
<li style="list-style-type: none;">
<ul>
<li>GMSL: good for ADAS-scale automotive.</li>
</ul>
</li>
</ul>
<p><!-- /wp:list-item --><!-- wp:list-item --></p>
<ul>
<li style="list-style-type: none;">
<ul>
<li>Ethernet + Holoscan: the right architecture for distributed, multi-sensor, safety-critical AI platforms.</li>
</ul>
</li>
</ul>
<p><!-- /wp:list-item --></p>
<p><!-- /wp:list --><!-- wp:paragraph --></p>
<p>Tauro Technologies’ DA322 Holoscan MIPI Adapter provides the bridge into this model &#8211; not as a devkit locked in the lab, but as a product that can be deployed today.</p>
<p>Interested to know more? <a href="https://taurotech.com/support/" target="_blank" rel="noreferrer noopener">Get in touch</a> with us for details.</p>
<p><!-- /wp:paragraph --><!-- wp:paragraph --></p>
<p><strong>Goodbye GMSL. Hello Holoscan.</strong></p>
<p><!-- /wp:paragraph --><!-- wp:paragraph --></p>
<p><!-- /wp:paragraph --></p>

<!-- wp:paragraph -->
<p></p>
<!-- /wp:paragraph --><p>The post <a href="https://taurotech.com/blog/holoscan-platform-for-robotics-and-edge-ai/">Holoscan Platform for Robotics and Edge AI</a> appeared first on <a href="https://taurotech.com">Tauro Technologies</a>.</p>
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			</item>
		<item>
		<title>Leveraging COM Express and COM-HPC for AI Workloads</title>
		<link>https://taurotech.com/blog/com-express-for-ai-workloads/?utm_source=rss&#038;utm_medium=rss&#038;utm_campaign=com-express-for-ai-workloads</link>
		
		<dc:creator><![CDATA[Sargis Ghazaryan]]></dc:creator>
		<pubDate>Tue, 18 Jul 2023 05:06:21 +0000</pubDate>
				<category><![CDATA[Artificial Intelligence]]></category>
		<category><![CDATA[Embedded Systems]]></category>
		<category><![CDATA[Hardware design]]></category>
		<category><![CDATA[AI]]></category>
		<category><![CDATA[AI Accelerator]]></category>
		<category><![CDATA[Axelera]]></category>
		<category><![CDATA[Blaize]]></category>
		<category><![CDATA[COM Express]]></category>
		<category><![CDATA[COM-HPC]]></category>
		<category><![CDATA[Edge AI]]></category>
		<category><![CDATA[Embedded systems]]></category>
		<category><![CDATA[Hailo]]></category>
		<category><![CDATA[M.2]]></category>
		<guid isPermaLink="false">https://taurotech.com/?p=2931</guid>

					<description><![CDATA[<p>Leveraging COM Express and COM-HPC for AI Workloads As the demand for artificial intelligence continues to rise in various industries, from healthcare and finance to manufacturing and autonomous vehicles, industrial computers face the challenge of optimizing AI workloads. Developers are constantly seeking efficient and scalable solutions to solve these challenges. One such solution is using&#8230;</p>
<p>The post <a href="https://taurotech.com/blog/com-express-for-ai-workloads/">Leveraging COM Express and COM-HPC for AI Workloads</a> appeared first on <a href="https://taurotech.com">Tauro Technologies</a>.</p>
]]></description>
										<content:encoded><![CDATA[
<h1 class="wp-block-heading has-text-align-center">Leveraging COM Express and COM-HPC for AI Workloads</h1>



<p class="wp-block-paragraph">As the demand for artificial intelligence continues to rise in various industries, from healthcare and finance to manufacturing and autonomous vehicles, industrial computers face the challenge of optimizing AI workloads. Developers are constantly seeking efficient and scalable solutions to solve these challenges. One such solution is using COM Express , a standardized form factor that can be used as a flexible computing platform for various AI workloads.</p>



<p class="wp-block-paragraph">With the ability to choose from wide variety of CPUs and the flexibility to right-size CPU to target various AI workloads, COM Express empowers organizations to create efficient, scalable, and cost-effective AI solutions. In addition to harnessing the advantages of COM Express, developers can leverage additional AI accelerators to further optimize the solutions.  COM-HPC,  a new specification, further enables enhanced performance and scalability for high-performance computing applications.</p>



<p class="wp-block-paragraph">The Intel Alder Lake x86 CPU is an ideal solution for COM Express modules targeting AI workloads due to built-in AI acceleration with Intel Deep Learning Boost technology. This integrated AI capability allows for efficient execution of AI workloads, such as neural network inference and deep learning tasks. By leveraging the built-in AI accelerator, COM Express modules based on Alder Lake can provide optimized performance for AI applications without the need for additional external accelerators.</p>



<h2 class="wp-block-heading"><strong>What is COM Express?</strong></h2>



<p class="wp-block-paragraph">COM Express is a highly integrated and compact computer on module that is designed to offer scalability and flexibility by providing a standardized form factor and interface for integrating different processor architectures and I/O configurations. Introduced by the PCI Industrial Computer Manufacturers Group in 2005, COM Express provides a single circuit board with integrated RAM.</p>



<p class="wp-block-paragraph">This family of modular, small form factor modules has gained significant traction in various industries, including automation, gaming, retail, transportation, robotics, and medical fields. With eight different types, four sizes, and three major revisions, COM Express promotes vendor technology reuse while catering to mid-range edge processing and networking requirements.</p>



<p class="wp-block-paragraph">The key differentiator of COM Express from traditional single-board computers (SBCs) lies in its ability to plug off-the-shelf modules into custom carrier boards designed for specific applications. This enables an upgrade path for the CPUs while keeping the carrier board intact. By using a custom COM Express carrier board, all necessary signals can be efficiently routed to the peripherals, while COM Express processor modules serve as the main controller. These advanced features ensure the versatility and adaptability of COM Express for diverse application requirements.</p>



<h2 class="wp-block-heading"><strong>Comparing COM-HPC with COM Express</strong></h2>



<p class="wp-block-paragraph">COM-HPC is an evolution of the COM Express standard, uniquely tailored to address the demands of high-performance computing applications. With its focus on enhanced performance, scalability, and advanced features, COM-HPC caters to the same applications and markets as COM Express, but with notable differentiators. It boasts higher-end CPUs, expanded memory capacity, and increased and faster I/O capabilities. It&#8217;s essential to emphasize that COM-HPC does not aim to replace COM Express, rather the two standards exist as distinct entities in the field of embedded computing, offering developers a broader spectrum of choices to meet specific application requirements.</p>



<p class="wp-block-paragraph">COM-HPC brings significant improvements over COM Express for AI workloads, particularly in terms of PCIe lanes and PCIe generation support:</p>



<ul class="wp-block-list">
<li>Increased PCIe Lanes: One of the key advantages of COM-HPC over COM Express is the availability of more PCIe lanes. COM Express has a limited number of PCIe lanes, which can restrict the connectivity options and the number of I/O interfaces or accelerators that can be integrated. In contrast, COM-HPC modules provide a higher number of PCIe lanes, allowing for more extensive connectivity and the integration of multiple high-speed devices.</li>



<li>PCIe Gen4/5 Support: Another crucial enhancement in COM-HPC is the support for PCIe Gen4 and Gen5, whereas COM Express supports up to PCIe Gen3. PCIe Gen4 and Gen5 offer higher data transfer rates and improved bandwidth compared to Gen3. This is particularly advantageous for AI workloads that require fast data movement between the CPU, GPU, storage devices, and other peripherals.</li>
</ul>



<p class="wp-block-paragraph">In summary,  newer generation processors, paired with higher data rates, dramatically lower the size, power and cost requirements of the systems required to perform the AI tasks.</p>



<h2 class="wp-block-heading"><strong>The Advantages of Choosing COM Express for AI Workloads</strong></h2>



<p class="wp-block-paragraph">COM Express offers several distinct advantages when it comes to AI workloads. As a flexible and scalable platform, it provides developers to adapt their AI systems according to specific requirements like CPU performance, power requirements. They can then design a carrier board that integrates the module with additional AI-specific components, such as AI accelerators. Below is the block diagram example of COM Express platform with AI Accelerator.</p>


<div class="wp-block-image is-resized">
<figure class="aligncenter size-full"><img loading="lazy" decoding="async" width="2044" height="2164" src="https://taurotech.com/wp-content/uploads/2023/07/Block-Diagram.drawio.png" alt="Block diagram of a COM Express Module architecture showing connections to an AI Accelerator, PCIe slots, MiniPCIe for LTE/WiFi, and I/O ports like HDMI, Dual USB 3.0, and Dual GbE RJ-45." class="wp-image-2955" style="aspect-ratio:0.9445378151260504;width:511px;height:auto" srcset="https://taurotech.com/wp-content/uploads/2023/07/Block-Diagram.drawio.png 2044w, https://taurotech.com/wp-content/uploads/2023/07/Block-Diagram.drawio-768x813.png 768w, https://taurotech.com/wp-content/uploads/2023/07/Block-Diagram.drawio-1451x1536.png 1451w, https://taurotech.com/wp-content/uploads/2023/07/Block-Diagram.drawio-1934x2048.png 1934w" sizes="(max-width: 2044px) 100vw, 2044px" /><figcaption class="wp-element-caption">&nbsp;<strong>Figure 1: </strong>COM Express AI Compute System</figcaption></figure>
</div>


<p class="wp-block-paragraph">Here are the key advantages of choosing COM Express (or COM-HPC) for AI workloads:</p>



<ul class="wp-block-list">
<li>Flexibility and Scalability: COM Express allows developers to choose from a wide range of CPU options. Such kind of flexibility allows them to choose the module that best matches the computing needs of their AI workloads. Whether it&#8217;s a complex neural network inference or deep learning task, the platform can be customized to deliver optimal performance.</li>



<li>Modular Design: COM Express follows a modular design approach with a separate CPU module and carrier board. This modularity simplifies system customization and future upgrades. Developers can easily swap out or upgrade the CPU module without redesigning the entire system, saving time and effort while adapting to evolving AI requirements.</li>



<li>Streamlined Integration: COM Express adheres to industry-standard form factors and interfaces, ensuring compatibility across different vendors. This standardized approach simplifies system integration, reducing development complexity and time to market. Developers can focus on optimizing their AI algorithms and software, confident that the hardware integration will be seamless.</li>



<li>Rich Connectivity Options: COM Express provides a wide array of interfaces, including Ethernet, USB, PCIe, and DisplayPort interfaces. These interfaces enable effortless integration with various peripherals, sensors, and external devices commonly used in AI applications. The rich connectivity options enhance data I/O capabilities, facilitating efficient communication and interaction within the AI system.</li>



<li>Long-Term Availability and Support: COM Express offers long-term availability and support, ensuring continuity for AI deployments. This is particularly crucial for industries that rely on stable and long-lasting AI systems. With a consistent platform and extended availability, developers can plan for long-term deployment and maintenance, with access to software updates and technical assistance.</li>



<li>Cost Optimization: COM Express provides a cost-effective solution for AI workloads. By leveraging COM Express, developers can save on development costs and reduce time to market. The modular design allows for efficient resource allocation, ensuring optimal performance while minimizing unnecessary expenses.</li>



<li>Time to Market:  Since the computer modules are widely available in the embedded marketplace, COM Express enables developers to focus on the IO needs, the addition of accelerators, the AI models and application software.</li>
</ul>



<h2 class="wp-block-heading"><strong>Real-World Applications of COM Express for AI Workloads</strong></h2>



<p class="wp-block-paragraph">As stated above, COM Express modules offer immense potential for developers to optimize AI workloads on industrial computers, leading to transformative impacts and various implications for cost-effective solutions and large-scale deployments. Let&#8217;s delve into real-world examples and insights to showcase the significance of this optimization trend.</p>



<p class="wp-block-paragraph">In the field of autonomous vehicles, this optimization trend allows autonomous vehicles to navigate complex environments, enhancing safety and efficiency. By leveraging COM Express modules, developers can achieve cost-effective solutions by utilizing existing industrial computers and upgrading them with optimized AI capabilities, resulting in large-scale deployments of autonomous vehicles across transportation networks.</p>



<p class="wp-block-paragraph">Industrial automation is another area where COM Express systems can revolutionize AI workloads. By optimizing AI algorithms on industrial computers using COM Express modules, developers can achieve significant cost savings and efficiency gains in manufacturing processes. For instance, AI-powered computer vision systems can inspect and detect defects in real-time, improving quality control and reducing production costs. The use of COM Express modules enables industrial computers to handle these AI workloads effectively, making cost-effective solutions viable for large-scale deployment in manufacturing facilities.</p>



<p class="wp-block-paragraph">In the healthcare sector, COM Express systems can optimize AI workloads on industrial computers to improve diagnostics, patient monitoring, and personalized treatment. For example, by leveraging COM Express systems, developers can enable industrial computers to process complex medical imaging data and apply AI algorithms for more accurate and timely diagnosis. This optimization trend in AI workloads allows healthcare providers to deliver cost-effective, benefiting patients globally.</p>



<h2 class="wp-block-heading"><strong>What to choose</strong></h2>



<p class="wp-block-paragraph">AI accelerators are paired with COM Express module on the carrier as separate modules or integrated directly into the carrier board&#8217;s design. This modular approach provides scalability and flexibility, allowing system designers to customize AI processing capabilities to meet the specific requirements of their applications. It also enables easy upgrades or replacements of AI accelerators without having to modify the entire system, making it both cost-effective and future-proof. AI accelerators such as <a href="https://www.blaize.com/">Blaize</a>, <a href="https://hailo.ai/">Hailo</a> or <a href="https://www.axelera.ai/">Axelera</a> paired with COM Express module can provide significant benefits. For example, combining Axelera M.2 AI Edge accelerator module with COM Express Carrier board can achieve up to 120 TOPS of AI performance with the flexibility of switching between the CPU families for optimized compute needs.</p>



<p class="wp-block-paragraph">These accelerators are specifically designed to enhance AI workloads and provide optimized compute capabilities compared to GPUs. This level of compute power can greatly benefit vision processing applications, which often require intensive computations for tasks such as object detection and classification.</p>



<h2 class="wp-block-heading"><strong>Conclusion</strong></h2>



<p class="wp-block-paragraph">COM Express and COM-HPC offer flexible and scalable platform to enable various AI workloads, allowing developers to customize their systems based on CPU performance, power requirements, and I/O interfaces. CPUs like Intel Alder Lake integrated into COM Express modules provide efficient AI execution, integrated graphics performance, enhanced compute density, ecosystem support, and broad connectivity options. The combination of the CPU with optional AI Accelerator delivers optimized performance, reducing costs and enabling efficient large-scale AI deployments.</p>



<p class="wp-block-paragraph">With the Tauro Technologies’ team of electronic engineers and designers it becomes possible to design and deploy comprehensive AI processing systems based on x86 and ARM CPUs paired with various AI Accelerators. This strategic approach helps bring down costs and ensures the right balance between compute power and AI processing needed for the system.  We can customize the I/O as well as the footprint to fit your application requirements.</p>



<p class="wp-block-paragraph">Interested to know more?&nbsp;<a href="https://taurotech.com/contact-us/" target="_blank" rel="noreferrer noopener">Get in touch</a>&nbsp;with us for details.</p>



<p class="wp-block-paragraph"></p>
<p>The post <a href="https://taurotech.com/blog/com-express-for-ai-workloads/">Leveraging COM Express and COM-HPC for AI Workloads</a> appeared first on <a href="https://taurotech.com">Tauro Technologies</a>.</p>
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		<title>Use of GPUs in Edge AI Computing:</title>
		<link>https://taurotech.com/blog/gpu/?utm_source=rss&#038;utm_medium=rss&#038;utm_campaign=gpu</link>
		
		<dc:creator><![CDATA[Paul Kuepfer]]></dc:creator>
		<pubDate>Tue, 27 Sep 2022 15:09:45 +0000</pubDate>
				<category><![CDATA[Embedded Systems]]></category>
		<category><![CDATA[Hardware design]]></category>
		<category><![CDATA[AI Accelerators]]></category>
		<category><![CDATA[Edge AI]]></category>
		<category><![CDATA[GPU Computing]]></category>
		<category><![CDATA[GPU Integration]]></category>
		<category><![CDATA[NVIDIA GPUs]]></category>
		<category><![CDATA[System on Module]]></category>
		<guid isPermaLink="false">https://taurotech.com/?p=2219</guid>

					<description><![CDATA[<p>Use of GPUs in Edge AI Computing An Artificial Intelligence (AI) accelerator accelerates artificial intelligence applications such as artificial neural networks and machine learning. In the last decade, graphics processing units (GPUs) have seen increasing adoption for these applications since they efficiently perform image processing and mathematical neural network calculations. Fortunately for AI development, GPU&#8230;</p>
<p>The post <a href="https://taurotech.com/blog/gpu/">Use of GPUs in Edge AI Computing:</a> appeared first on <a href="https://taurotech.com">Tauro Technologies</a>.</p>
]]></description>
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<h1 class="wp-block-heading has-text-align-center"><strong>Use of GPUs in Edge AI Computing</strong></h1>



<p class="wp-block-paragraph"></p>



<p class="wp-block-paragraph">An Artificial Intelligence (AI) accelerator accelerates artificial intelligence applications such as artificial neural networks and machine learning. In the last decade, graphics processing units (GPUs) have seen increasing adoption for these applications since they efficiently perform image processing and mathematical neural network calculations. Fortunately for AI development, GPU manufacturers such as NVIDIA are making GPUs that greatly enhance AI performance, opening the door to many new computing products at the edge.&nbsp; NVIDIA products have led the market with innovation and are widely used in AI computing. However, other specialty GPU providers offer enhanced performance on portions of AI computing, such as AI inferencing.&nbsp;</p>



<h2 class="wp-block-heading">What is a GPU?</h2>



<p class="wp-block-paragraph">A modern Graphical Processing Unit or GPU is similar to a CPU but makes use of parallel processing and is able to handle many processes and threads at the same time. Due to its parallel processing, a GPU is normally used for graphics processing and rendering.</p>



<p class="wp-block-paragraph">GPUs have been around since the 1970s, primarily used for arcade games such as Sea Wolf and Space Invaders. Graphics cards were not commonly used in PCs until the mid-1980s, when the NEC μPD7220A became the first processor with a Large Scale Integration circuit chip, making it the most popular GPU. The next significant innovation was in the 1990s with S3 Graphics making the S3 86C911. This new GPU used 2D acceleration to gain a massive performance increase compared to its competitors. Today, a GPU is one of the most crucial hardware components of computer architecture.</p>



<p class="wp-block-paragraph">Initially, the purpose of a video card was to take a stream of binary data from the central processor and render images to display. But modern graphics processing units are engaged in the most complex calculations, like big data research, machine learning, and AI.</p>



<p class="wp-block-paragraph">While AI has existed since the 1990s in inference and training, AI&nbsp;accelerators did not enter the market until 10 years ago, when the workloads of AI processes became more intensive. Since 2010, AI accelerators such as field-programmable gate arrays (FGPA) and customized application-specific integrated circuits, (ASIC) are being replaced by commercial GPUs, which offer faster time to market and lower development costs.&nbsp;</p>



<h2 class="wp-block-heading">The GPU Market </h2>



<p class="wp-block-paragraph">Currently, the GPU industry is dominated by three large companies: NVIDIA, Intel, and AMD. These companies have been around for the longest, with NVIDIA pioneering the discrete GPU market since 2000 and putting them into a firm leadership position.&nbsp; New entrants into the GPU market are picking a product niche and developing solutions that are efficient and designed to fill the appetite for higher performance with lower costs per watt of power. Up to 90% of the power consumed by an image processing application is accessing the RAM. Today, there are new entrants with differing approaches to building more efficient GPUs, including Mythic.AI, UntetherAI, Hailo, Blaize, etc., for edge AI computing.&nbsp; These companies focus on avoiding data transfer between computing and memory to drive efficiency.&nbsp;&nbsp;</p>



<h2 class="wp-block-heading"><strong>GPU vs CPU</strong></h2>



<p class="wp-block-paragraph">In the past, CPUs were used to process information for artificial intelligence. However, as GPUs have become more powerful over time, their ability to process more parallel information faster has made them a much better solution for AI.&nbsp;</p>



<figure class="wp-block-table"><table><tbody><tr><td></td><td>CPU</td><td>GPU</td></tr><tr><td>Amount of cores&nbsp;&nbsp;</td><td>10’s of cores</td><td>100’s to 1000’s of cores</td></tr><tr><td>Processing focus</td><td>Low latency</td><td>High throughput</td></tr><tr><td>Processing</td><td>Serial processing for many tasks</td><td>Excellent parallel processing of the same task</td></tr><tr><td>Parallel tasks</td><td>Performs multiple processes at once</td><td>Performs 1000’s of processes at once</td></tr><tr><td>Architecture</td><td>MIMD (Multi-instruction, multiple data streams)</td><td>SIMD (Single instruction, multiple data streams)&nbsp;or&nbsp;SIMT (Single instruction, multiple threads)&nbsp;</td></tr><tr><td>Cost and Availability</td><td>More readily available, more widely manufactured, and cost-effective for consumer and enterprise use</td><td>Still significantly more expensive, this cost rises more when talking about a GPU built for specific tasks like mining or analytics.</td></tr><tr><td>Compatibility</td><td>Not every system or software is compatible with every processor.</td><td>Compatible with all systems</td></tr></tbody></table></figure>



<h2 class="wp-block-heading">Integrating a GPU into an application:</h2>



<p class="wp-block-paragraph">GPUs are typically shipped as modules to be easily implemented into various applications. Chip-down GPU designs are intensive hardware and software projects; also, GPU vendors historically will only support Tier 1 customers and projects and encourage the rest of the applications to design a carrier that integrates their modules.&nbsp;</p>



<p class="wp-block-paragraph">Here are some common GPU module form factors:</p>



<h3 class="wp-block-heading">PCIe</h3>



<ul class="wp-block-list">
<li>This is the first and still most common form factor for GPU modules and is easily integrated with common PC motherboards with up to x16 Gen5 PCIe connections. However, the disadvantage is that they are large and bulky for many edge AI applications and typically require forced air to cool them.</li>
</ul>



<h3 class="wp-block-heading">MXM (Mobile Express Module)</h3>



<ul class="wp-block-list">
<li>As the name indicates, the MXM form factor was developed to offer graphics processing module capabilities to smaller mobile computers such as laptops. It is also commonly used in edge SFF computing applications in markets such as military, medical, and transportation. The modules can be air cooled or conduction cooled.</li>
</ul>



<h3 class="wp-block-heading">M.2</h3>



<ul class="wp-block-list">
<li>The M.2 standard replaces the mSATA standard and offers size and speed advantages for storage.&nbsp; Gen4 PCIe x4 connections to the processor allow it to be also widely used for other computing functions, including GPS, LTE, IO, and smaller GPUs by vendors such as Hailo.&nbsp;&nbsp;</li>
</ul>



<h3 class="wp-block-heading">E1.S EDSFF (Enterprise and Datacenter Small Form Factor)</h3>



<ul class="wp-block-list">
<li>E1.S is the choice of next-generation storage modules.&nbsp; It offers greater density and performance than the M.2 and other earlier form factors.</li>
</ul>



<ul class="wp-block-list">
<li>Although it is being deployed in the datacenter server industry, it has not yet replaced M.2 as a standard in SFF Edge Computing.&nbsp;&nbsp;</li>



<li>Blaize is an example of a GPU being deployed in the ES.1 SFF, enabling up to 512 TOPS in a 1U server and 16-64 TOPS in an SFF computer.</li>
</ul>



<h3 class="wp-block-heading">SOM (System on Modules)</h3>



<ul class="wp-block-list">
<li>System on Modules has been made popular for industrial edge computing by NVIDIA in products such as JETSON.</li>



<li>Embedded ARM processors in the SOM enable a solutions provider to build a smaller, low-cost edge AI or graphics processing computer without needing a separate embedded CPU.</li>
</ul>



<h3 class="wp-block-heading">Chip-Down</h3>



<ul class="wp-block-list">
<li>With many edge platforms, it is the most cost-effective to design a solution with a ‘chip-down’ GPU and a ‘chip-down’ CPU.&nbsp; Tauro Technologies has designed these systems for several of the GPU vendors mentioned above.</li>
</ul>



<h2 class="wp-block-heading">GPU integration into a carrier board:</h2>



<p class="wp-block-paragraph">System design takes many factors into consideration, including cooling, power, I/O, storage, processing, etc., and each system requirement is different. Typically, GPU modules that are not chip-down are integrated into a main board or carrier board that has been customized to meet the application requirements.&nbsp;&nbsp;</p>



<p class="wp-block-paragraph">There are 2 main types of processors integrated into carrier boards:</p>



<ul class="wp-block-list">
<li>Intel x86: Due to the engineering complexity of Intel chip-down designs, many edge AI applications choose to use COMe or COM-HPC client-based modules to simplify their carrier design projects. Although the material cost of the module is higher than a chip-down solution, unless the product reaches modest volumes, it is more cost-effective to design with an x86-based module.&nbsp;</li>
</ul>



<ul class="wp-block-list">
<li>ARM-based processors: ARM processors are typically lower cost and take less power, making them ideal for many computer vision products when paired with a GPU.&nbsp; Since there are few modules available based on open standards, most ARM-based products are custom designed with a chip-down processor such as NXP Cortex or Layerscape.&nbsp;&nbsp;</li>
</ul>



<h2 class="wp-block-heading">Summary:</h2>



<p class="wp-block-paragraph">The advent of AI is opening the door for application-specific GPUs that are finely tuned to the objectives of the project. Tauro Technologies has broad experience implementing edge computers optimized for the application. If you wish to discuss a customized high-volume platform or a system which takes advantage of commercially available hardware and tools, <a href="https://taurotech.com/contact-us/">reach out to us</a>.</p>
<p>The post <a href="https://taurotech.com/blog/gpu/">Use of GPUs in Edge AI Computing:</a> appeared first on <a href="https://taurotech.com">Tauro Technologies</a>.</p>
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		<title>Advantages in Machine Vision on the Edge</title>
		<link>https://taurotech.com/blog/vision-processing/?utm_source=rss&#038;utm_medium=rss&#038;utm_campaign=vision-processing</link>
		
		<dc:creator><![CDATA[Paul Kuepfer]]></dc:creator>
		<pubDate>Mon, 29 Mar 2021 21:24:42 +0000</pubDate>
				<category><![CDATA[Embedded Systems]]></category>
		<category><![CDATA[Hardware design]]></category>
		<category><![CDATA[Deep Learning Inference]]></category>
		<category><![CDATA[Edge AI]]></category>
		<category><![CDATA[Intel Movidius Myriad X]]></category>
		<category><![CDATA[Machine Vision]]></category>
		<category><![CDATA[Robotics AI Applications]]></category>
		<category><![CDATA[Vision Processing Unit]]></category>
		<guid isPermaLink="false">https://taurotech.com/?p=1192</guid>

					<description><![CDATA[<p>Advantages in Machine Vision on the Edge Efficiency of Artificial intelligence (AI) utilizing vision systems to manage autonomous vehicles and robots is at the core of well designed unmanned system.&#160; Putting that AI processing close to the machine vision cameras and time-of-flight sensors, offers a breakthrough for a wide range of manufacturing and logistics applications.&#160;&#8230;</p>
<p>The post <a href="https://taurotech.com/blog/vision-processing/">Advantages in Machine Vision on the Edge</a> appeared first on <a href="https://taurotech.com">Tauro Technologies</a>.</p>
]]></description>
										<content:encoded><![CDATA[
<h1 class="wp-block-heading has-text-align-center">Advantages in Machine Vision on the Edge</h1>



<p class="wp-block-paragraph">Efficiency of Artificial intelligence (AI) utilizing vision systems to manage autonomous vehicles and robots is at the core of well designed unmanned system.&nbsp; Putting that AI processing close to the machine vision cameras and time-of-flight sensors, offers a breakthrough for a wide range of manufacturing and logistics applications.&nbsp; To optimize the power of AI requires high compute overhead to manage the large data streams of vision systems. &nbsp; This function is traditionally performed on the centralized GPU system&nbsp; of the robot or UAV.&nbsp; One of the most interesting AI recent developments&nbsp; is the <a href="https://www.intel.com/content/www/us/en/products/docs/processors/movidius-vpu/myriad-x-product-brief.html">Intel® Movidius™ Myriad™ X</a> Vision Processing Unit (VPU). This device can take up to six camera inputs, perform deep learning inference functions and sensor input processing at the edge while using under five watts of power.&nbsp;</p>



<p class="wp-block-paragraph">The Intel® Movidius™ Myriad™ X VPU pushes the inferencing for deep learning to the system edge and enables applications to avoid costly processing on standard or high-performance computing (HPC) systems. Myriad X VPU can be used as the main processor in low power embedded systems by using the embedded ARM processor or as a coprocessor/accelerator engine to perform the deep learning inference.&nbsp;</p>



<p class="wp-block-paragraph">One use case for Myriad X could be to offload the AI and computer vision work from a system using a low-cost, low-power, low performance platform to process sensor inputs. The deep learning inferencing in these systems may be performed in a central server or the cloud, with data passing back-and-forth between the sensors and the servers. Performing the AI on the edge avoids the data transfer between the sensors and the main processors which cuts down the overall overhead and latency.</p>



<p class="wp-block-paragraph">The Myriad X VPU can be used as the main processor for an embedded device such as smart surveillance camera or, bringing it back to the industrial arena, robotic manipulators or grippers with vision systems. This kind of standalone system can avoid the cost of additional servers.</p>



<p class="wp-block-paragraph">Whether you select a standalone or co-processor type architecture will depend on your overall system design. Tauro Technologies has experience with both options and we would be happy to discuss the design tradeoffs of one approach versus the other with your specific application in mind.</p>



<h2 class="wp-block-heading">Which Applications Could Benefit?</h2>



<p class="wp-block-paragraph">The range of applications that can take advantage of a combination of machine vision, AI and depth sensing is immense. Robots can map places and tasks, such as figuring out how best to avoid people. Other uses include pick-and-place, combined assembly and inspection, and moving shelves of items from one location to another. There are many ways to implement these complementary technologies and trends evolve quickly in machine vision. The team at Tauro Technologies has integrated hardware platforms that combine the power of the Intel Movidius Myriad X VPU and its neural engine with the enhanced depth sensing achieved by integrating both ToF sensors and customized stereo vision and is ready to speak with you about your applications. <a href="https://taurotech.com/contact-us/">Get in touch</a> with us for details.</p>
<p>The post <a href="https://taurotech.com/blog/vision-processing/">Advantages in Machine Vision on the Edge</a> appeared first on <a href="https://taurotech.com">Tauro Technologies</a>.</p>
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