Serial Protocols & Their Uses: I2C, UART, SPI
Serial communications protocols are vital to embedded systems. While UART, I2C, and SPI have been used for short-distance device communication for decades, the benefits are not entirely apparent.
In order to connect peripherals to a computer, one of the following protocols is typically employed: a Universal Asynchronous Receiver Transmitter, (UART) Inter-Integrated Circuit, (I2C) or Serial Peripheral Interface (SPI). This blog will compare and contrast the features of each protocol and help you determine the best fit for your application.
UART
Universal Asynchronous Receiver Transmitter (UART) is an asynchronous serial communication device with its roots dating back to the telegraph. There is no clock signal to synchronize or validate the data transmitted from the transmitter and received by the receiver (Asynchronous Serial Communication). It sends 1 bit at a time from least significant to most significant and uses start and stop bits to enable precise clocking. During packet transmission, UART uses what is called a parity bit, to enable checking if the information has changed during transmission.
In addition, data transmission between devices can be in simplex, half-duplex, or full duplex modes.
Data is transmitted at baud rate measured in bits per second – some of the standard baud rates are 4800 bps, 9600 bps, 19200 bps, 115200 bps etc. Out of these, 9600 bps baud rate is the most commonly used.
UARTs must be set for the same bit speed, character length, parity, and stop bits for proper operation on the transmit and receive side. If the receiving UART detects mismatched settings a flag is sent in the host system memory to indicate a failure.
The data in UART serial communication is organized into blocks called Packets or Frames. The structure of a typical UART data packet or the standard framing of the data is shown in the following table:
| Frame | Start | Data | Parity | Stop |
|---|---|---|---|---|
| Length | 1 bit | 5 to 9 bits | 0 to 1 bits | 1 to 2 bits |
Advantages:
- Management is straightforward through hardware. It is utilized by standard protocols including RS-232/485/422.
- Long-distance up to 1km for RS-422/485 buses.
- Requires only two wires for full-duplex data transmission (other than power lines).
- Parity bit ensures basic error checking is integrated into the data packet frame.
- No need for clock or any other timing signal.
Disadvantages:
- Communication is only between two devices where the baud rate, data bit count, parity bit, and stop bit count need to be identical.
- Typically the size of the data frame is limited to only 9 bits (8 data bits, no parity bit and one stop bit).
- Overrun errors if the buffer space is insufficient.
- Size of data in the frame is limited.
I2C
Unlike UART, an Inter-Integrated Circuit is a synchronous serial communication interface and utilizes the system clock. It means that data bits are transferred one by one at regular intervals of time set by a SCL clock line. It is used primarily for short distance, intra-board communication between low speed controllers and processors and is ideal for applications that link up to many components on a bus. Although I2C is typically implemented with a single master and multiple slaves on the bus, it can also be implemented with multiple masters. Each slave device has a unique address and I2C enables the master to send and request data from a particular slave device utilizing a start bit to the slave address.
I2C only uses two wires to transmit data between devices:
- SDA (Serial Data) – The line for the master and slave to send and receive data.
- SCL (Serial Clock) – The line that carries the clock signal (common clock signal between multiple masters and multiple slaves).
The structure of a typical I2C Data Packet or the standard framing of the data is shown in the following table (Note: The bold signals are sent by slave and the other signals by master):
| Frame | Start | Address | Read/Write | ACK/NACK | Data 1 | ACK/NACK | Data 2 | ACK/NACK | Stop |
|---|---|---|---|---|---|---|---|---|---|
| Length | 7 to 10 bits | 1 bit | 1 bit | 8 bits | 1 bit | 8 bits | 1 bit |
Advantages:
- Addressing function enables multiple masters and slaves.
- Control a network of devices with only 2 I/O pins.
- Simple mechanism for validation of data transfer.
- I2C networks are easy to scale. New devices can simply be connected to the two common I2C bus lines.
- No need for prior agreement on data transfer rate as in UART communication.
Disadvantages:
- Slower speed (up to 100 kbit/s in standard mode, 400 kbit/s in fast mode)
- Half-duplex interface.
- Only one slave can be addressed at a time.
SPI
The Serial Peripheral Interface (SPI) is also a synchronous serial communication device which is used primarily for short distance communication. The main difference between SPI and I2C is that SPI uses a full-duplex communication with master-slave topology. Similar to I2C , SPI can be used to access multiple slave devices.
At the beginning of communication, the bus master configures the clock (typically 50 MHz) and sends data to the slave. During a single SPI clock cycle, a full duplex of data transmission is completed. Unlike UART, there are no start and stop bits – this enables continuous data transmission and the communication achieves higher speeds than I2C and UART.
The maximum data rate limit is not specified in the SPI interface. Standard data rates include 10 Mbps transfer rate with some devices reaching 100Mbps transfer rate.
The SPI bus consists of 4 signals below:
- Master – Out / Slave – In (MOSI)
- Master – In / Slave – Out (MISO)
- Serial Clock (SCLK)
- Chip Select (CS) or Slave Select (SS)
Depending on the values of Clock Polarity (CPOL) and Clock Phase (CPHA), there are 4 modes of operation of SPI:
- Mode 0 is active when Clock Polarity is LOW and Clock Phase is LOW (CPOL = 0 and CPHA = 0). Data sampled on rising edge and shifted out on the falling edge.
- Mode 1 is active when Clock Polarity is LOW and Clock Phase is HIGH (CPOL = 0 and CPHA = 1). Data sampled on the falling edge and shifted out on the rising edge.
- Mode 2 is active when Clock Polarity is HIGH and Clock Phase is LOW (CPOL = 1 and CPHA = 0). Data sampled on the falling edge and shifted out on the rising edge.
- Mode 3 is active when Clock Polarity is HIGH and Clock Phase is HIGH (CPOL = 1 and CPHA = 1). Data sampled on the falling edge and shifted out on the rising edge.
The structure of a typical SPI data packet or the standard framing of the data is shown in the following image:
Advantages:
- Full-duplex is default for the SPI protocol.
- Slaves do not require a unique address.
- Not limited to 8-bit word size.
- Real-estate savings on embedded boards.
- High data transfer speed.
- No need for individual addresses for slaves as CS or SS chip-select lines are used.
- Only one master device is supported, removing the possibility of conflicts.
- SPI uses less power than I2C.
Disadvantages:
- No protocol-level error checking function and no hardware slave acknowledgement.
- Short distances (up to 10m).
- Each additional slave requires an additional dedicated pin on the master for CS or SS.
- There is no acknowledgement mechanism and hence there is no confirmation of data receipt.
- Slowest device determines transfer speed.
Summary
In general, you can use UART if you are looking for a simple connection between 2 devices, I2C if you are connecting several devices on the same bus, and SPI becomes the ideal choice if you require a faster interface. Whether you need UART’s tried and true operation, or want to utilize the expansion offered by I2C or the high speed of SPI, Tauro Technologies can implement a system using the most appropriate interface for your project.
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