Ethernet Sensor Bridges and the Next Generation of Edge AI Systems

For more than a decade, embedded vision systems have relied on two dominant interfaces: MIPI-CSI and GMSL. These standards were good enough for automotive ADAS, drones, and early robotics. They offered reliability and adequate bandwidth at a small scale.

But the requirements have changed:

• Defense programs now field distributed sensor fusion across vehicles, ships, and unmanned systems.
• Robotics are moving from lab prototypes with two or three cameras to fleets with dozens of vision, radar, and lidar nodes.
• Healthcare and industrial inspection demand higher bandwidth, tighter synchronization, and safety-certifiable architectures.

In this environment, MIPI and GMSL show their limits.

Why It’s Time to Move Beyond MIPI-CSI and GMSL

MIPI-CSI:

• Short reach – designed for PCB-level connections, not vehicle or platform-scale systems. The cable length is limited to around 30cm.
• Point-to-point only – every new sensor requires a direct link, adding complexity as counts grow.
• Scaling beyond a few links requires custom bridges or FPGAs.

GMSL:

• Built for automotive, with EMI resilience and reliable coax transmission.
• Practical for 2–6 cameras, but scaling further is complex.
• Proprietary PHYs lock you to vendors.
• No multicast support: every stream is point-to-point.
• Synchronization limited by PHY-level timing, not system-wide clocks.

Shared flaw: both push sensor data through the CPU before the GPU. That means extra latency, jitter from OS scheduling, and additional CPU heat – already the thermal bottleneck in many rugged systems.

For defense and robotics, these constraints can be showstoppers.

Ethernet + Holoscan Changes the Model

NVIDIA’s Holoscan SDK and Thor AGX platform shift sensor ingress from CPU-managed links to Ethernet with GPUDirect RDMA. This architecture streams data directly into GPU memory, bypassing the CPU entirely.

Engineering implications:

• Lower Latency
  Removing CPU buffering eliminates context switches and driver overhead. Benchmarks show up to 5× lower latency compared to USB, and ~1.5× lower compared to MIPI. For radar, EO/IR, or autonomy pipelines where microseconds matter, this is decisive.
• Determinism
  With no OS scheduling in the path, jitter drops significantly. IEEE 1588-2019 PTP synchronization aligns multiple boards to sub-microsecond precision. Distributed arrays of sensors can now operate in phase across vehicles or unmanned platforms.
• Thermal headroom
  CPUs no longer manage sensor ingress. That frees cycles, reduces utilization, and most importantly, cuts heat generation. In rugged defense and robotics deployments, where cooling is the hardest part of the design, this translates directly into more reliable systems.
• Scalability
  Adding sensors means adding Ethernet bandwidth or switch ports. The same network that supports four cameras today can support forty tomorrow – without redesigning CPU pipelines.
• Multicast
  A single camera feed can be consumed by multiple GPU pipelines simultaneously – one for navigation, one for targeting, one for operator display. GMSL and MIPI topologies can’t do this natively.
• Safety and Security
  Ethernet brings built-in support for MACSec, packet watermarking, redundancy, and hooks for SIL-2 compliance. These features are not bolt-ons but part of the end-to-end architecture.

This is not just a faster pipeline. It is a cleaner, more efficient system design for multi-sensor AI workloads.

What is NVIDIA Holoscan?

Holoscan is a multimodal computing platform designed for the edge, providing an accelerated end-to-end software stack for scalable, software-defined, real-time processing of streaming data.

Holoscan Sensor Bridge Software

  Holoscan Sensor Bridge software consists of two main components:

• NVIDIA Holoscan SDK – Build high-performance streaming applications by composing modular operators into customizable pipelines
• Holoscan Sensor Bridge host software – Build custom pipelines and process data from network-connected sensors using ready-to-use operators for tasks such as image conversion, signal processing, inference, and visualization

Holoscan applications separate the main application and define the data pipeline with the necessary operators in a configure method.

With the User Space API, HSB connects sensor operation with the Linux endpoint in a way that developers focus on the pipeline and the operations required for the specific application.

Holoscan Sensor Bridge Performance

Embedded systems require high-resolution, high-frame-rate data with low latency and precise synchronization. Holoscan Sensor Bridge (HSB) meets these requirements, delivering up to 5 times lower latency than USB cameras (119ms) and 1.5 times lower latency than MIPI cameras (37ms). By leveraging RDMA and camera over Ethernet, HSB transfers data directly into GPU memory with virtually zero CPU utilization, enabling real-time processing and faster system response.

HSB enhances embedded system performance by replacing traditional kernel-space camera drivers with user-space APIs, eliminating the need for separate drivers for camera and control functionalities. This approach simplifies development complexity, allowing developers to focus on application logic. HSB’s modular design supports various Image Signal Processor (ISP) options, including NVIDIA CUDA-based ISPs, soft-ISP implementations on HSB hardware, and internal ISPs found on NVIDIA Jetson AGX and IGX platforms.

Precision Time Protocol (PTP)

One of the key features supported by HSB is Precision Time Protocol (PTP), which enables the HSB to synchronise its internal clock with the host system. HSB achieves synchronisation accuracy of 1µs and better, allowing developers to precisely track exactly when each event occurs and align data across multiple sources.

Sensor Bridges: Why They Matter

Holoscan defines the architecture, but engineers still need a way to connect physical sensors to an Ethernet network. This is where sensor bridges come in.

• NVIDIA provides the GPUs and SDK.
• Lattice offers a Holoscan devkit – useful for exploration, but built around dual FPGAs and not production-ready.
• What the market lacks is a deployable bridge: something engineers can prototype with in the lab, then bolt directly into a rugged system without redesign.

That gap is exactly what Tauro Technologies’ DA322 Holoscan MIPI Adapter fills.

DA322 Holoscan MIPI Adapter

The DA322 provides a compact, rugged bridge from MIPI sensors into an Ethernet-based Holoscan pipeline

Unlike devkits, the DA322 is production-ready. It supports two distinct use cases:

1. 1. Prototyping: Engineers can connect up to four MIPI sensors, stream over 10GbE, and validate Holoscan pipelines quickly.

1. 1. Deployment: The same hardware can be mounted in defense platforms, robotic fleets, or medical devices without a redesign. The DA322 is only 75×45×15mm and can be sized down/up depending on product requirements.

Roadmap: Beyond 4-Lane MIPI

The DA322 demonstrates the model with four MIPI CSI-2 D-PHY lanes. However, some real-world systems require a mix of sensor types and counts. Tauro Technologies has deployed customized systems with I/O, including:

• • GMSL bridges:  to migrate automotive-grade sensors into Ethernet topologies without redesign.

• • Radar/Lidar bridges:  extending the same low-latency Ethernet path to RF and optical sensing modalities.

• • Custom I/O variants:  bespoke designs with the right mix of ingress interfaces for primes and OEMs.

Product design and flexibility are Tauro Technologies’ specialty – sensor ingress tailored to your exact requirements.

Why It Matters for Your Next System

For engineers building the next generation of edge AI systems, the benefits are clear:

• • Remove the CPU bottleneck: Lower latency, lower jitter, and reduced thermal load.

• • Scale without rework: Ethernet networks scale naturally as sensor counts grow.

• • Meet determinism and safety requirements: PTP sync, SIL-2 compliance, built-in security.

• • Prototype and deploy on the same hardware: Faster development cycles and lower NRE.

GMSL and MIPI fit the previous generation. Ethernet + Holoscan is right for the next one.

Conclusion

Every major industry that outgrew point-to-point links – from datacenters to telecom to automotive – standardized on Ethernet. Sensor fusion for AI is following the same trajectory.

• • MIPI-CSI: good for phones and embedded modules.

• • GMSL: good for ADAS-scale automotive.

• • Ethernet + Holoscan: the right architecture for distributed, multi-sensor, safety-critical AI platforms.

Tauro Technologies’ DA322 Holoscan MIPI Adapter provides the bridge into this model – not as a devkit locked in the lab, but as a product that can be deployed today.

Interested to know more? Get in touch with us for details.

Goodbye GMSL. Hello Holoscan.

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In embedded systems, where software and hardware are tightly coupled, replacing obsolete hardware is rarely trivial. Whether due to component going EOL, performance shortfalls, or evolving application needs, the cost of re-engineering and re-qualifying systems from scratch can be substantial. Larger systems have years of design and validation testing prior to their release, and changes to mission-critical embedded systems are expensive and risky. 

That’s where software-compatible drop-in replacements come in – offering a smart, strategic solution that preserves system functionality, minimizes downtime, and avoids expensive revalidation cycles.

What Is a Software-Compatible Drop-In Replacement?

A software-compatible drop-in replacement hardware is engineered to mimic the form, fit, and function of the original device, while maintaining backward compatibility at the software and hardware interface level. These replacements integrate seamlessly into the existing systems without requiring changes to the interfacing hardware, firmware, or application software.

Achieving software-compatible hardware replacements requires a rigorous engineering process that ensures:

• Electrical and pin-level compatibility
• API and driver-level consistency
• Form factor and mechanical interface integrity
• System-level behavior across operating conditions

The compatibility ensures the replacement hardware behaves predictably within the larger system – allowing customers to extend the life of their platforms without rewriting the software stack or re-qualifying the hardware.

TauroTech’s Methodology for Developing Drop-In Replacements

In creating a drop-in replacement for an embedded system, an approach involving various engineering disciplines and extensive testing is imperative. Engineers must thoroughly understand the existing system to be able to design a matching replacement, build a prototype, and ensure it meets all requirements before moving into production.

Pre-Design Evaluation: Ensuring Technical and Functional Alignment

Evaluation is crucial for assessing the feasibility and the characteristics of new components, modules, or interfaces. This phase includes rigorous black-box functional system analysis and careful component selection.

Black-Box Functional System Analysis: This methodical approach is essential for understanding and evaluating system’s behavior and functionality without being concerned with its internal structure. Key points include defining functional requirements and operational characteristics through datasheets and documentation, mapping inputs to outputs, and examining system behavior under various usage models and corner-case scenarios.

Critical Component Selection: In this phase, it is imperative to thoroughly research available components in the market and select solutions that meet or exceed the specifications and performance of the original components. Critical components such as microprocessors, sensors, and power supplies must unequivocally meet performance and reliability criteria of the system being replaced.

Design Phase: Building a Compatible Replacement

The design phase focuses on creating a fully integrated drop-in replacement by aligning electrical, digital, mechanical, and software elements. The goal is to ensure the design fits, functions, and communicates just like the original – without requiring changes to the broader system.

Electrical Design: Engineers develop schematics and board layout that replicate the original hardware’s power, signaling, and interface requirements. Emphasis is placed on ensuring pin compatibility, stable power delivery, and reliable operation within the system.

FPGA and Digital Design: When programmable logic is needed, FPGAs or SoCs are selected based on performance, compatibility, and long-term support. Custom logic is developed to match system behavior and ensure seamless integration.

Mechanical Design: Mechanical aspects such as dimensions, mounting, and connector placement are carefully matched to the original. The design also accounts for thermal performance and reliability in the intended environment.

Software Development: Low-level software – including drivers and firmware – is developed or adapted to ensure the new hardware integrates seamlessly into the existing software stacks. This ensures system behavior remains consistent and reliable.

API and Interface Compatibility: User-facing APIs and communication protocols are preserved to avoid changes to application code. Compatibility at this level is key to minimizing integration time and risk.

System-Level Test & Form/Fit/Function Compatibility Validation 

Thorough validation at the system level is essential to ensure that drop-in replacements not only function independently but also operate reliably as part of the larger system.

System-level testing evaluates the replacement component in the context of the complete system, verifying correct behavior under real-world operating conditions. This process includes checking interoperability with other subsystems, confirming that timing, interfaces, and performance targets are met, and identifying any integration issues that might not be apparent during isolated component testing. For drop-in replacements, this step is critical to ensuring that legacy software and hardware continue to function as intended with the new module.

Form, fit, and function validation ensures that the replacement meets physical, mechanical, and functional expectations without requiring system modifications.

• Form confirms that the dimensions, shape, and footprint match the original.
• Fit ensures proper alignment with enclosures, connectors, and mounting points.
• Function verifies that the component performs its intended role within the system – electrically, thermally, and functionally – without impacting other components.

Design Validation and Acceptance Documentation

Design Validation Testing (DVT) and Acceptance Test Procedures (ATP) play complementary roles in the qualification and production of drop-in replacements, ensuring both the integrity of the design and the consistency of manufactured units.

DVT is performed during development to verify that the design meets all functional, electrical, mechanical, and environmental requirements. This includes defining the test environment, identifying key features to be validated, applying structured test methodologies, and confirming the design’s ability to meet performance specifications.

Acceptance Test Procedures (ATP) are implemented at the production stage to validate that each unit manufactured meets the defined quality and performance criteria. ATPs are derived from customer-approved specifications and simulate key aspects of real-world operation to confirm that the assembled product conforms to expectations. These procedures serve as a final gate before shipment and may include automated test sequences, functional checks, and go/no-go criteria for each production lot.

Lifecycle Engineering & Long-Term Support

Longevity of Supply: Longevity of supply is crucial for ensuring that products remain viable and supported in the market for their intended lifespan. TauroTech offers strategies to manage component availability, including notifying customers about product end-of-life (EOL) and suggesting options such as purchasing customer-bonded stock or updating the product in lock-step with customer evaluation and approval process. Bonded stock involves reserving inventory for a specific customer, ensuring their long-term supply needs are met, while revision-locked production ensures no software and design changes are made without the customer’s formal sign-off. This customer-inclusive approach aims to minimize supply chain disruptions and ensure that product changes correspond to their needs and standards before being applied.

Longevity of Repair: Longevity of repair in embedded systems refers to the expected duration of the repair capability, which is crucial in industries where products that are no longer produced may require maintenance or replacements. Factors such as spare part availability, manufacturer support, design features, and industry regulations need to be considered for decision-making. Tauro Technologies’ repair strategy is based on mutual agreements with customers, ensuring repair services and support for a specified period. To fulfill this commitment, Tauro Technologies holds customer-bonded stock, allowing for necessary repairs even when parts become unavailable. At the end of the contract, all stock is returned to the customer.

Roadmap Planning: Roadmap planning involves creating a structured plan to meet changing customer needs. Tauro Technologies ensures a smooth transition to new products, involving customers in decision-making processes and ensuring alignment with customer expectations. Tauro Technologies also supports the re-qualification process and offer guidance, focusing on integrating the replacement component by engaging customers and prioritizing their needs. 

Why Tauro Technologies?

With over 15 years of embedded system expertise and full in-house capabilities, Tauro Technologies is uniquely positioned to deliver high-reliability, software-compatible hardware replacements that are thoroughly tested to ensure reliability across all operational scenarios – including edge cases and extreme conditions.

We support customers in defense, medical, transportation, and robotics sectors with:

• Hardware replacements designed for Form/Fit/Function and Software compatibility
• Integrated electrical, mechanical, and firmware engineering under one roof
• Manufacturing through AS9100/ISO9001-certified partners
• Rapid prototyping and system-level validation for faster deployment

Looking to replace aging hardware with a fully compatible solution—backed by better supply chain control, and long-term support? Let’s talk.

Reach out at info@taurotech.com or visit www.taurotech.com to start the conversation.

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An embedded system refers to a specialized computer system designed to perform dedicated functions within a larger mechanical or electrical system. It typically consists of a combination of hardware and software components tailored to perform specific tasks or functions. Embedded systems play a crucial role in mobile robotics, UAV construction and edge AI. Such systems are characterized by their real-time operation, reliability and efficiency in executing predetermined functions, often with limited resources such as processing power, memory and energy. In remote areas, for example, everything is run off batteries or generators. Consequently, many embedded systems are engineered to incorporate various techniques to extend battery life. The others simply need to consume less energy based on other factors. As a result, there’s an increasing demand for designs that minimize energy usage while maintaining high performance. In this article we are going to elaborate on the strategies for achieving low-power designs and highlight their significance in embedded systems.

The Need for Low-Power Design

Low-power design involves strategies and approaches aimed at decreasing the energy usage of electronic devices and refers especially to the underlying embedded systems upon which such devices operate. Examples of such devices are battery-powered devices, processors, IoT wireless sensor networks and many more. Through the application of low-power design methods, engineers can create high-quality and reliable equipment which consume considerably less energy without any indication of performance degradation. The need for low-power devices arises from several factors:

• Power sources are often limited and the disruption in the energy supply can result in adversities. This is particularly true for battery-powered devices in military situations where power outages can cost lives. That’s why defense is always looking for lower power consumption in airborne and ground vehicle applications.
• Portability of everyday devices (notebooks, smartphones, etc.) which will have prolonged battery life is one of the concerns of device manufacturing companies. In today’s world, it is a common tendency for customers to have a preference for devices with extended battery life.
• Low-power design will certainly have a huge positive impact on the environment as a large amount of electricity is wasted through devices connected to the grid. The decrease in the electricity consumption of such devices will result in less costs and will cause less damage to the environment.
• In embedded systems, high power consumption can result in a significant amount of heat generation damaging the system components. The reduction of generated heat is one of the concerns for military equipment production. As a fact, the overall decrease in power consumption will considerably reduce the generated heat. Consequently, initially employing low-power design techniques will protect the system from unexpected side effects due to thermal issues.
• Less heat generation can lead to improved performance and reliability of the embedded system. Overheating can cause performance degradation or even hardware failures, so by keeping temperatures within acceptable limits, low-power designs contribute to overall reliability and durability of the system.

Key Principles of Low-Power Design

To grasp the fundamental principles of low-power design, it’s imperative to dive into power consumption basics, sleep modes, clock gating techniques and voltage scaling strategies. This exploration will shed light on how each aspect contributes to the creation of energy-efficient embedded systems.

Power Consumption Basics

Power consumption indicates how much electrical energy a device or a system uses to perform its functions or operations. There are two primary sources of power consumption in electronic devices – static and dynamic. Devices consume static power when idle and dynamic power during active use. Reducing both static and dynamic power consumption is essential for creating low-power designs achieved through the means of efficient components and optimized circuits. Understanding consumption allows informed decisions on resource allocation and environmental impact mitigation. Embracing energy-efficient practices drives towards sustainability while ensuring reliable access to necessities.

Power Management and Sleep Modes

Implementing sleep modes and power states can significantly reduce power consumption in embedded systems. Sleep modes enable devices to enter low-power states when not performing tasks, therefore conserving energy. Power states define consumption levels based on system activity and performance needs. Selecting appropriate modes ensures optimal power usage and performance while maintaining efficiency.

All sleep modes are accessible from active mode, where the CPU executes application code. Upon entering sleep mode, program execution halts, and the device relies on interrupts or a reset for waking up. The application code determines the timing and choice of sleep mode. Enabled interrupts from peripherals and reset sources can return the CPU from sleep to active mode. Furthermore, power reduction registers offer means to halt individual peripheral clocks via software control. This action freezes the peripheral’s current state, eliminating its power consumption. Consequently, power usage is minimized in both active mode and idle sleep modes, facilitating more nuanced power management than sleep modes alone.

Here are several examples of low-power modes:

Sleep Mode: In this mode, the device reduces its power consumption by powering down non-essential components while retaining data in memory. The CPU typically enters a low-power state, halting its operation until an external event, such as a button press or an interrupt, wakes it up.

Deep Sleep Mode: This mode is an even lower power state compared to sleep mode. In deep sleep, the device shuts down most of its non-essential functions, including reducing power to the CPU and peripherals. This mode is commonly used in battery-powered devices to prolong battery life during extended periods of inactivity.

Standby Mode: This mode is similar to sleep mode but may involve a slightly higher level of power consumption. In this mode, the device reduces power to most components, but some essential functions remain active to enable quick recovery. It’s commonly used in devices like TVs and remote controls, where rapid responsiveness is necessary.

Clock Gating for Dynamic Power Reduction

Clock gating is a technique aimed at reducing dynamic power consumption by selectively switching off unnecessary clock signals to registers using control signals, all while ensuring functional correctness. By turning off the clock to idle parts of a device, it conserves power, directing it only to active components and minimizing waste. Implementing clock gating in embedded systems can substantially reduce power usage, particularly in devices with numerous components or intricate functionalities.

Typically, the assignment to a register might be conditional, as depicted above. When EN is 0, the clocks to the registers can be stopped otherwise, the registers will switch states on each clock cycle, which dissipates power.

Voltage Scaling Strategies

Voltage scaling strategies in low-power design involve adjusting the core supply voltage to align with the system’s performance needs. Decreasing voltage decreases power consumption, but it can impact performance, necessitating a careful balance between the two. Techniques like adaptive voltage scaling and dynamic voltage scaling are commonly used in embedded systems to find this balance, often coupled with frequency scaling to maintain acceptable performance levels while reducing power consumption. Dynamic Voltage and Frequency Scaling (DVFS) is a power management technique that adjusts the voltage and frequency of the device’s CPU dynamically based on workload demands. During periods of low activity, the CPU voltage and frequency are decreased to save power, while they are increased during high-demand tasks to maintain performance. These strategies are particularly crucial in portable devices where battery life is a primary concern.

Design Techniques for Low-Power Embedded Systems

When thinking about the low-power embedded systems, there is no single rule that applies to every type of requirement. Rather it is a combination of a system design, circuit design and firmware design all combined and working together to deliver the best performance per watt. Embedded engineers construct embedded systems using various low-power techniques, allowing for adaptable control over device’s energy usage based on its activities and operating patterns. 

Hardware Techniques for Low-Power Design

In the realm of low-power embedded system design, the selection of hardware components plays a pivotal role. Optimal choices can significantly influence the system’s overall power consumption. This section will delve into various hardware techniques, such as component selection for low-power embedded systems, employing energy-efficient microcontrollers and processors, and integrating sensors designed for minimal energy consumption.

Energy-efficient component selection: Picking the right components is crucial for any electronic system, affecting design, layout, and power usage. When it comes to low-power designs, choosing components wisely is even more critical. To reduce power consumption in embedded systems, we need to focus on factors like operating voltage, idle/standby current, and overall efficiency of the components. Opting for parts with lower consumption can significantly cut down on energy usage in the system.

Energy-efficient microcontroller and processor selection: Embedded systems rely heavily on microcontrollers and processors, and their power efficiency is crucial in determining overall power usage. When choosing a microcontroller or a processor, prioritize components with low operating voltages, effective sleep modes, and power-saving capabilities like clock gating and voltage scaling. Incorporating these features ensures decreased power consumption without compromising performance, making them ideal choices for energy-conscious designs.

One example of a low-power AI accelerator is Hailo-15 that can process multiple video streams in real time on a single device with robust onboard network connectivity. It offers very high AI performance of 26 TOPS and very low power consumption of 2.5W which makes it perfect for AI computing and for mission-critical applications with power consumption reduced by approximately 70% compared to GPU based solutions. Another example is Intel’s hybrid CPU architecture, which combines “P cores” for high-intensity computational tasks and “E cores” for handling less-intensive tasks while maximizing energy-efficiency, addressing the requirements of modern computing.

Energy-efficient process node selection: When talking about semiconductor ICs, selecting newer devices with 5nm technology node vs 10nm reduces power by 40%, 3nm improves 45% over 5nm, 14nm reduces power by 50% over 28nm etc. Power efficiency can be dramatically improved when using IC built on top of latest technology node.

Energy-efficient FPGA design: Field-Programmable Gate Array (FPGA) devices offer the advantage of flexibility and customization in hardware design. In certain applications, this flexibility can lead to power reduction by combining multiple functions into a single FPGA device rather than using discrete components.

Energy-efficient sensor selection: Sensors play a crucial role in embedded systems, gathering data from the surroundings or user interactions. Opting for sensors with minimal power demands that can transition into low-power modes when inactive is a key. Furthermore, explore sensors equipped with built-in power management functionalities like automatic sleep modes and adjustable sample rates to enhance energy efficiency even further. By selecting sensors with these capabilities, overall power consumption in the system can be significantly reduced, ensuring efficient operation.

Software Techniques for Low-Power Design

It is generally more effective to begin monitoring the energy consumption as early as possible to access the potential risks of high energy consumption points during the implementation process. When the software is already implemented and integrated, it is usually more difficult and expensive to eliminate such issues. On the other hand, energy consumption levels are directly proportional to computational complexities and improving one will result in indirect improvement of the other. Therefore, it is a good idea to introduce several software development techniques to achieve low-power in embedded systems.

Code optimization: Optimize algorithms to reduce the overall CPU utilization. Try using efficient algorithms and data structures to reduce the computational complexity. Frequently, there is a tradeoff between faster processing/larger code size vs slower processing/smaller code size. Usually, optimizing a code for speed vs size is a better choice.

Event-Based Task Scheduling: Events are generated to trigger the system to perform some work. Once the processor finishes the requested task, it goes back to idle state allowing it to remain in low-power modes for longer durations. Incorporating sleep modes in the code putsthe processor or specific peripherals into low-power states during periods of inactivity. Use of efficient task scheduling algorithms minimizes wake-up times and ensures that tasks are executed in a power-efficient manner.

Optimized Data and I/O Access: Minimizing unnecessary data transfers and using efficient data structures to reduce power consumption during memory access operation such as unnecessary copying of data, especially when large blocks of memory are allocated. Reducing the frequency of I/O operations and using techniques such as batch processing to minimize power consumption during data transfers. Optimizing cache usage to minimize memory accesses and reduce power consumption associated with accessing external memory.

Code Profiling and Optimization: Profiling code to identify power-hungry sections and optimizing them to reduce power consumption without sacrificing performance is a major area for optimization. Additionally, compilers that optimize code for low-power execution can significantly reduce energy consumption by minimizing unnecessary operations and maximizing sleep modes utilization. Debugging tools that provide insights into power consumption behavior during development help identify and solve power inefficiencies early in the design process.

Using Low-Power Communication Protocols

The adoption of low-power communication protocols within embedded systems is paramount for achieving energy efficiency while maintaining reliable data transmission. This section aims to offer insights into energy-efficient communication standards and wireless protocols customized for low-power applications.

Wireless Protocols for Low-Power Design

Wireless communication is gaining popularity in embedded systems for its adaptability and scalability. However, without energy-efficient implementation, it can lead to considerable power consumption. Several wireless protocols, tailored for low-power applications, have emerged to address this concern, including:

• BLE is designed for low-power devices and applications with infrequent data transmission.
• NB-IoT technology is designed to provide low-power wide area network (LPWAN) connectivity for IoT devices. This means that NB-IoT devices have very low-power consumption compared to traditional cellular devices, which enables them to operate on a single battery charge for years.
• Z-Wave is a highly efficient and low-energy technology. While the smart home hub requires a constant power supply to keep the network up and running, many Z-Wave devices operate on battery power alone for a year or more before requiring replacement.
• LoRa is ideal for IoT applications requiring low data rate transmission over long distances.
• ZigBee is a low-power, low-data-rate wireless communication protocol commonly used in home automation and industrial control systems.

Conclusion

Tauro Technologies can dramatically reduce system cost, size, and power requirements through optimized hardware and software design, and meticulous component selection. Our diverse portfolio of high-efficiency modules and integrated systems is engineered to meet the most demanding industrial standards. Contact us to explore how we can enhance your systems.

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What is an indoor location tracking system?

Indoor location tracking system locates and tracks the movement of people or objects inside buildings. Indoor location tracking is enabled by indoor positioning systems, a network of electronic devices and computer software used to locate people or objects where and when GPS is inaccurate or fails completely. Furthermore, the accuracy of the GPS is often times less than what’s required to track objects indoors. Although the terms “indoor location tracking” and “indoor positioning” are interchangeable, there are currently many different types of technologies used to calculate and provide real-time location data.

In this blog post, we’ll talk about the changing world of indoor location tracking systems, delve into the countless applications in the industry, uncover the benefits they bring, and speculate on the exciting future prospects of indoor location tracking systems.

How do indoor location tracking systems work?

Indoor location tracking systems, also known as indoor positioning systems (IPS) detect and track object location using a variety of sensors. IPS normally uses transmitters (e.g. tags, badges) and receivers (e.g. beacons)  to provide precise location information for tracked assets. Transmitters identify people or assets and can be attached, embedded, or worn. Receivers capture signals from transmitters and send the data to the central management system. These systems are widely used across various industries to track personnel, valuable equipment, materials, and vehicles.

GPS and IPS services are sometimes mixed up due to similar tasks and acronyms. GPS works best outdoors, relying on satellites for location. Indoors, GPS signals are unreliable and lack precision in crowded spaces. Ongoing research may bring new indoor GPS options in the future.

Technologies Used in Indoor Location Tracking Systems

An indoor positioning system helps find people or objects inside a building. It has two main parts: anchors and position tags. Anchors, like beacons or relays, are placed strategically around the premises. People or things carry position tags. Anchors actively locate these tags or provide location/context information for the device.

There are different ways to track objects indoors: , Wi-Fi, Magnetic Field Detection, Near Field Communication (NFC), Ultra-wideband (UWB) radio, and UHF RFID. Each method has its own level of accuracy, cost, power usage, and ease of use. Since there’s no obvious best choice, sometimes it’s difficult to determine which technology is most suitable. Let’s look at the most common options.

• Bluetooth Based Indoor Positioning

Bluetooth based indoor positioning is a really promising technology for expanding indoor tracking in various fields, such as logistics, healthcare, manufacturing, retail, warehouses, and smart buildings.

Bluetooth proves to be a highly effective choice for indoor localization, offering real-time meter-level accuracy with cost-effective and power-efficient hardware. Its simplified deployment is due to technological standardization, ensuring cross-vendor device compatibility. The widespread adoption of Bluetooth in existing devices further contributes to its ease of use, making it a versatile solution for diverse applications such as logistics, healthcare, manufacturing, retail, warehouses, and smart buildings.

BLE (Bluetooth Low Energy) IPS solution uses beacons or sensors to locate and detect transmitting Bluetooth devices such as track labels, and smartphones throughout the indoor area. Location data obtained from sensors or sent from beacons to mobile devices is then absorbed by various applications and translated into insights that support multiple location-aware use cases.

Bluetooth based solution supports two architectures, one based on the radio signal’s angle of arrival at the anchor point, the other based on its angle of departure.

In AoA based scenario, a mobile device has a tag that sends a Bluetooth signal with direction information. Antenna arrays measure these signals to find the angle of arrival using a network-based engine. The slight phase differences in the signals received by antennas help calculate the angle of arrival.

With AoD, a mobile device receives Bluetooth signals from antenna arrays. The device uses signal measurements to find the direction from which the signal departs the antenna array. The slight phase differences in signals received help calculate the angle of departure given the antenna array geometry is known.

To pinpoint a mobile device indoors, a single anchor with multiple antennas can be used to figure out its location relative to the anchor. For higher accuracy, multiple stationary anchors with multi-antenna arrays are employed. By triangulating signals from several anchors and finding their intersection, the exact position of the device can be calculated.

• Ultra-wideband (UWB) indoor positioning

UWB uses a train of impulses instead of a modulated sine wave to transmit information. It’s perfect for precision applications because of its unique characteristic. Since the pulse rising edge is extremely sharp it allows the receiver to accurately measure the arrival time of the signal. Furthermore, the pulses are extremely narrow, usually lasting less than two nanoseconds.

The signals’ nature allows UWB pulses to be resistant to multipath effects and be identified even in noisy environments. UWB has significant ranging capability advantages over traditional narrowband signals due to these traits. Also, due to the strict spectral mask, the transmit power lies at the noise floor, which means that UWB does not interfere with other radio communication systems operating in the same frequency bands. It just increases the overall noise floor, a principle that is very similar to spread spectrum technologies (CDMA).

• Wi-Fi indoor positioning

The use of Wi-Fi can enable the detection and tracking of people, devices, and assets. Indoor positioning can be easily calculated using existing Wi-Fi access points. Wi-Fi can be found everywhere, particularly indoors, used by nearly all wireless devices and network infrastructures – including smartphones, computers, IoT devices, routers, APs, and more. To detect and locate Wi-Fi transmitters, such as smartphones and tracking tags, Wi-Fi indoor positioning solutions employ existing Wi-Fi access points or Wi-Fi enabled sensors. WI-Fi-based positioning systems can use different methods to determine the location of the devices.

Wi-Fi Positioning Using Access Points: Access points are installed indoors to locate devices and use already existing Wi-Fi infrastructure. Transmissions from nearby Wi-Fi devices, both on and off the network, can be detected by building APs. The location data is sent to a server and central IPS which are used to determine the position of a device.

Wi-Fi Positioning Using Sensors: Sensors that are deployed in fixed position indoors passively detect and locate transmissions from smartphones, asset tracking tags and other Wi-Fi devices. The sensor’s collected location information is then transmitted to a server and incorporated by the central indoor positioning system (IPS).

Wi-Fi positioning methods often rely on the Received Signal Strength Indicator (RSSI) to figure out where the device is located. In applications using RSSI, several Wi-Fi access points, set in fixed positions, pick up signals from transmitting Wi-Fi devices and measure the strength of those signals. The location engine then uses multilateration algorithms to analyze this data and estimate the position of the transmitting devices.

Indoor Location Tracking Benefits

• Enhanced User Convenience

This system expands the comfort of the users in indoor areas, for example, thanks to IPS, users no longer need to indicate their current location, when moving from one point to another in the indoors. Also, they no longer need to worry about doors, turns or other obstacles, because now they can see them in advance on the map in real-time. Modern day warehouses are like complex living organisms with rapidly moving machinery, products, robots, and personnel. Real-time tracking of the locations of the moving pieces is necessary for efficient and effective functioning on a minute-by-minute basis.

In an application developed by Tauro Technologies used UWB radio based solution to assist firefighters and first-responders on the scene during an incident. Fast, accurate decisions can save lives, keep the first-responders safe and are dependent on accurate real-time information to make mission critical split second decisions. Tauro Technologies developed the hardware and triangulation software system for indoor location tracking to meet those requirements.

• Exclusion of possible human errors

Asset tracking also eliminates potential human errors. People can often get tired or have a lapse in judgment and accidentally misplace valuable assets or leave a highly sensitive location unstaffed. Indoor location tracking systems can provide alerts when people or assets leave a predefined area also known as geofencing. Users can opt to receive an email, text or voice notification if someone or something enters or leaves the area.

• Swift Incident Response

Indoor location tracking ensures the safety by providing real-time location data during emergencies. Lone workers, when out of communication, can trigger assistance requests, allowing security and emergency services to pinpoint their exact location. Leadership can identify the nearest security officers to a reported incident and efficiently direct them for intervention.

• Location-based marketing

The fusion of indoor navigation and positioning creates location-based marketing opportunities. Imagine tailoring a more personalized experience and special offers when shoppers linger at the pasta aisle or greet stadium visitors with personalized messages based on ticket sales data. This not only enhances user engagement but also increases revenue and profits. Offering marketing opportunities through push notifications to exhibitors, sponsors, or partners makes your venue more appealing and has the potential to boost your ROI.

Indoor Location Tracking Use Cases

The indoor positioning system is a reliable and convenient modern solution that can be used in various positioning solutions such as Asset tracking​, Item finding, Point of interest (POI) information, access control and security, people tracking and consumer behavior analysis, proximity marketing.

Below are some examples of indoor positioning system applications:

• Airport and Hospitality: Airports and hotels can track heavy equipment, tools, passenger baggage and visitors to improve daily operations, increase safety, and increase customer satisfaction.
• Medical Institutions and Healthcare: High-quality healthcare services allow patients to get the treatments they need without potentially harmful delays. By using this technology, staff, patients, and equipment like beds and wheelchairs can be easily located. It means better attendance checking, effective supervision, and better equipment maintenance are at your fingertips.
• Parking: Indoor location systems can be used to guide drivers to available parking spaces in indoor parking garages or lots.
• Warehouse: Real-time package location, inventory monitoring, and forklift high-precision positioning bring valuable information into the ERP and provide reliability and safety into warehouses.
• Museum: Mobile navigation, precise positioning, and low-cost tags bring new values to tourism location services. IPS can be used to enhance the visitor experience in museums by providing location-based information and interactive exhibits.

Challenges of Indoor Location Tracking Systems

Indoor navigation presents typical challenges in contrast to outdoor environments, where GPS technology is prevalent. The complex task of indoor positioning is made worse by the building layouts, which require specialized solutions to address the unique intricacies of navigating within enclosed spaces.

Here are some representations of the challenges of Indoor Location Tracking Systems and their solutions:

• Complex Building Layouts

Challenge: Large public places are often complicated with many floors, making it hard to keep track of and update the tracking information. These places change a lot due to renovations or temporary setups, so we need navigation systems that can adapt quickly in real-time.

Solution: Employing indoor mapping tools that facilitate collaboration and crowd-sourced mapping can play a crucial role in preserving accurate and current layouts. These tools empower users and venue owners to actively participate in the mapping process, guaranteeing the continued relevance and precision of the navigation system.

• Signal Interference

Challenge: In areas with high device density, the abundance of devices and wireless networks may cause signal interference. Such interference can compromise the reliability of indoor positioning technologies, leading to navigation inaccuracies and inconsistencies.

Solution: Implement machine learning techniques to filter noise and interference, enhancing indoor tracking performance. By combining machine learning with BLE and UWB technologies, an adaptive and interference-resistant solution can be achieved, significantly improving indoor tracking performance in challenging environments.

• Battery Consumption

Challenge: Indoor navigation apps often drain device batteries quickly, posing an issue for users without easy access to charging.

Solution: Optimizing the indoor navigation app’s energy consumption is crucial. Developers should focus on reducing unnecessary background processes and utilizing efficient programming techniques. Additionally, incorporating low-power mode options can help extend device battery life while using the navigation application.

Conclusion

Tauro Technologies’ experience in RF communications, power management as well as firmware and software design enables the development of reliable and energy efficient location tracking systems. Tauro Technologies has experience in a wide variety of applications including military, scientific, medical, industrial robotics, and communications. Get in touch with us for more information.

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As the demand for artificial intelligence continues to rise in various industries, from healthcare and finance to manufacturing and autonomous vehicles, industrial computers face the challenge of optimizing AI workloads. Developers are constantly seeking efficient and scalable solutions to solve these challenges. One such solution is using COM Express , a standardized form factor that can be used as a flexible computing platform for various AI workloads.

With the ability to choose from wide variety of CPUs and the flexibility to right-size CPU to target various AI workloads, COM Express empowers organizations to create efficient, scalable, and cost-effective AI solutions. In addition to harnessing the advantages of COM Express, developers can leverage additional AI accelerators to further optimize the solutions. COM-HPC, a new specification, further enables enhanced performance and scalability for high-performance computing applications.

The Intel Alder Lake x86 CPU is an ideal solution for COM Express modules targeting AI workloads due to built-in AI acceleration with Intel Deep Learning Boost technology. This integrated AI capability allows for efficient execution of AI workloads, such as neural network inference and deep learning tasks. By leveraging the built-in AI accelerator, COM Express modules based on Alder Lake can provide optimized performance for AI applications without the need for additional external accelerators.

What is COM Express?

COM Express is a highly integrated and compact computer on module that is designed to offer scalability and flexibility by providing a standardized form factor and interface for integrating different processor architectures and I/O configurations. Introduced by the PCI Industrial Computer Manufacturers Group in 2005, COM Express provides a single circuit board with integrated RAM.

This family of modular, small form factor modules has gained significant traction in various industries, including automation, gaming, retail, transportation, robotics, and medical fields. With eight different types, four sizes, and three major revisions, COM Express promotes vendor technology reuse while catering to mid-range edge processing and networking requirements.

The key differentiator of COM Express from traditional single-board computers (SBCs) lies in its ability to plug off-the-shelf modules into custom carrier boards designed for specific applications. This enables an upgrade path for the CPUs while keeping the carrier board intact. By using a custom COM Express carrier board, all necessary signals can be efficiently routed to the peripherals, while COM Express processor modules serve as the main controller. These advanced features ensure the versatility and adaptability of COM Express for diverse application requirements.

Comparing COM-HPC with COM Express

COM-HPC is an evolution of the COM Express standard, uniquely tailored to address the demands of high-performance computing applications. With its focus on enhanced performance, scalability, and advanced features, COM-HPC caters to the same applications and markets as COM Express, but with notable differentiators. It boasts higher-end CPUs, expanded memory capacity, and increased and faster I/O capabilities. It’s essential to emphasize that COM-HPC does not aim to replace COM Express, rather the two standards exist as distinct entities in the field of embedded computing, offering developers a broader spectrum of choices to meet specific application requirements.

COM-HPC brings significant improvements over COM Express for AI workloads, particularly in terms of PCIe lanes and PCIe generation support:

• Increased PCIe Lanes: One of the key advantages of COM-HPC over COM Express is the availability of more PCIe lanes. COM Express has a limited number of PCIe lanes, which can restrict the connectivity options and the number of I/O interfaces or accelerators that can be integrated. In contrast, COM-HPC modules provide a higher number of PCIe lanes, allowing for more extensive connectivity and the integration of multiple high-speed devices.
• PCIe Gen4/5 Support: Another crucial enhancement in COM-HPC is the support for PCIe Gen4 and Gen5, whereas COM Express supports up to PCIe Gen3. PCIe Gen4 and Gen5 offer higher data transfer rates and improved bandwidth compared to Gen3. This is particularly advantageous for AI workloads that require fast data movement between the CPU, GPU, storage devices, and other peripherals.

In summary, newer generation processors, paired with higher data rates, dramatically lower the size, power and cost requirements of the systems required to perform the AI tasks.

The Advantages of Choosing COM Express for AI Workloads

COM Express offers several distinct advantages when it comes to AI workloads. As a flexible and scalable platform, it provides developers to adapt their AI systems according to specific requirements like CPU performance, power requirements. They can then design a carrier board that integrates the module with additional AI-specific components, such as AI accelerators. Below is the block diagram example of COM Express platform with AI Accelerator.

Here are the key advantages of choosing COM Express (or COM-HPC) for AI workloads:

• Flexibility and Scalability: COM Express allows developers to choose from a wide range of CPU options. Such kind of flexibility allows them to choose the module that best matches the computing needs of their AI workloads. Whether it’s a complex neural network inference or deep learning task, the platform can be customized to deliver optimal performance.
• Modular Design: COM Express follows a modular design approach with a separate CPU module and carrier board. This modularity simplifies system customization and future upgrades. Developers can easily swap out or upgrade the CPU module without redesigning the entire system, saving time and effort while adapting to evolving AI requirements.
• Streamlined Integration: COM Express adheres to industry-standard form factors and interfaces, ensuring compatibility across different vendors. This standardized approach simplifies system integration, reducing development complexity and time to market. Developers can focus on optimizing their AI algorithms and software, confident that the hardware integration will be seamless.
• Rich Connectivity Options: COM Express provides a wide array of interfaces, including Ethernet, USB, PCIe, and DisplayPort interfaces. These interfaces enable effortless integration with various peripherals, sensors, and external devices commonly used in AI applications. The rich connectivity options enhance data I/O capabilities, facilitating efficient communication and interaction within the AI system.
• Long-Term Availability and Support: COM Express offers long-term availability and support, ensuring continuity for AI deployments. This is particularly crucial for industries that rely on stable and long-lasting AI systems. With a consistent platform and extended availability, developers can plan for long-term deployment and maintenance, with access to software updates and technical assistance.
• Cost Optimization: COM Express provides a cost-effective solution for AI workloads. By leveraging COM Express, developers can save on development costs and reduce time to market. The modular design allows for efficient resource allocation, ensuring optimal performance while minimizing unnecessary expenses.
• Time to Market: Since the computer modules are widely available in the embedded marketplace, COM Express enables developers to focus on the IO needs, the addition of accelerators, the AI models and application software.

Real-World Applications of COM Express for AI Workloads

As stated above, COM Express modules offer immense potential for developers to optimize AI workloads on industrial computers, leading to transformative impacts and various implications for cost-effective solutions and large-scale deployments. Let’s delve into real-world examples and insights to showcase the significance of this optimization trend.

In the field of autonomous vehicles, this optimization trend allows autonomous vehicles to navigate complex environments, enhancing safety and efficiency. By leveraging COM Express modules, developers can achieve cost-effective solutions by utilizing existing industrial computers and upgrading them with optimized AI capabilities, resulting in large-scale deployments of autonomous vehicles across transportation networks.

Industrial automation is another area where COM Express systems can revolutionize AI workloads. By optimizing AI algorithms on industrial computers using COM Express modules, developers can achieve significant cost savings and efficiency gains in manufacturing processes. For instance, AI-powered computer vision systems can inspect and detect defects in real-time, improving quality control and reducing production costs. The use of COM Express modules enables industrial computers to handle these AI workloads effectively, making cost-effective solutions viable for large-scale deployment in manufacturing facilities.

In the healthcare sector, COM Express systems can optimize AI workloads on industrial computers to improve diagnostics, patient monitoring, and personalized treatment. For example, by leveraging COM Express systems, developers can enable industrial computers to process complex medical imaging data and apply AI algorithms for more accurate and timely diagnosis. This optimization trend in AI workloads allows healthcare providers to deliver cost-effective, benefiting patients globally.

What to choose

AI accelerators are paired with COM Express module on the carrier as separate modules or integrated directly into the carrier board’s design. This modular approach provides scalability and flexibility, allowing system designers to customize AI processing capabilities to meet the specific requirements of their applications. It also enables easy upgrades or replacements of AI accelerators without having to modify the entire system, making it both cost-effective and future-proof. AI accelerators such as Blaize, Hailo or Axelera paired with COM Express module can provide significant benefits. For example, combining Axelera M.2 AI Edge accelerator module with COM Express Carrier board can achieve up to 120 TOPS of AI performance with the flexibility of switching between the CPU families for optimized compute needs.

These accelerators are specifically designed to enhance AI workloads and provide optimized compute capabilities compared to GPUs. This level of compute power can greatly benefit vision processing applications, which often require intensive computations for tasks such as object detection and classification.

Conclusion

COM Express and COM-HPC offer flexible and scalable platform to enable various AI workloads, allowing developers to customize their systems based on CPU performance, power requirements, and I/O interfaces. CPUs like Intel Alder Lake integrated into COM Express modules provide efficient AI execution, integrated graphics performance, enhanced compute density, ecosystem support, and broad connectivity options. The combination of the CPU with optional AI Accelerator delivers optimized performance, reducing costs and enabling efficient large-scale AI deployments.

With the Tauro Technologies’ team of electronic engineers and designers it becomes possible to design and deploy comprehensive AI processing systems based on x86 and ARM CPUs paired with various AI Accelerators. This strategic approach helps bring down costs and ensures the right balance between compute power and AI processing needed for the system. We can customize the I/O as well as the footprint to fit your application requirements.

Interested to know more? Get in touch with us for details.

The post Leveraging COM Express and COM-HPC for AI Workloads appeared first on Tauro Technologies.

Oscilloscopes are electronic devices used to observe and measure electrical signals. They are widely used in engineering, physics, and other fields to measure and analyze signals. Oscilloscopes display waveforms graphically, allowing users to see the shape, frequency, and amplitude of the signal being measured. In this blog post, we’ll highlight their critical characteristics for high-speed digital design and go over some factors to consider when choosing an oscilloscope.

What is an Oscilloscope?

An electronic device called an oscilloscope is used to analyze and display signal waveforms. It consists of a display, signal input channels, and controls for adjusting various settings. The oscilloscope creates a graph by tracking the voltage level of an electrical signal over time. This waveform can then be examined to find any potential issues or signal anomalies.

Oscilloscopes can be used to examine signals in a variety of ways. Oscilloscopes are great for analyzing, validating and debugging electrical systems as they allow to observe the signal change over time in the circuits. They may also be used to find defects in damaged radios, televisions, and other similar devices. Although coaxial cables are used to feed the signal into the probes of a standard oscilloscope, this does not mean that an oscilloscope can only measure electricity. You can use an oscilloscope to measure almost anything by connecting a transducer, which converts one kind of energy into another. For instance, you could study audio signals with an oscilloscope using a microphone (a transducer that converts sound energy into an electrical signal), study temperature changes with a thermocouple (a transducer that converts heat into electricity), or study vibrations with a piezoelectric transducer (which generates electricity when squeezed).

Types of Oscilloscopes

Oscilloscopes can be categorized into different types based on operation mode and the signal processing technologies, but there are two main types as every electronic equipment can be classified: analog and digital.

Analog Oscilloscopes

They are the earliest form of oscilloscopes and use a cathode ray tube (CRT) to display signals in real-time. Despite the advent of newer digital oscilloscopes, they are still used today for certain applications that require a fast response time and a high degree of accuracy.

Analog oscilloscopes (Figure 1) test equipment by directly applying measured signal voltage to its vertical axis, producing a visual representation on the CRT. These oscilloscopes have intensity and focus controls that can be easily adjusted to improve the display’s sharpness.

Figure 1: Tektronix 2445B

Digital Oscilloscopes

The main difference between analog and digital oscilloscopes is that in digital oscilloscopes, the analog signal is captured and converted into a digital signal using an analog to digital converter. In turn digital oscilloscopes classified into four parts:

• Digital storage oscilloscopes (DSO)
• Digital phosphor oscilloscopes (DPO)
• Mixed signal oscilloscopes (MSO)
• Digital sampling oscilloscopes

Digital storage oscilloscopes (DSO) (Figure 2) are the most basic form of digital oscilloscopes, its display typically relies on a raster-type screen rather than the luminous phosphor found in older analog oscilloscopes. It converts the analog signal into a digital format and stores it in its digital memory.

DSOs offer several advantages over analog ones. These include the ability to display a transient quantity over a long period of time, easy production of hard copies, signal processing and computation within the instrument, easy transfer of data to a computer, and the use of inexpensive LCD construction. The development of relatively cheap, accurate, and fast A/D converters has made DSOs available for laboratory and industrial use.

 Figure 2: InfiniiVision 4000 X-Series

Digital phosphor oscilloscope (DPO) (Figure 3) is a newer type of oscilloscope that was first introduced in 1998. Unlike digital storage oscilloscopes (DSOs) which use a serial-processing architecture, the DPO uses a parallel-processing architecture that allows it to deliver unique acquisition and display capabilities for accurately reconstructing a signal and capturing transient events.

After the data is stored in the memory unit, it follows two parallel paths. Firstly, a microprocessor processes the data acquired at each sampling instant according to the settings on the control panel and sends the processed signal to the instrument display unit. Additionally, a snapshot of the input signal is sent directly to the display unit at a rate of 30 images per second. This enhanced processing capability enables the DPO to have a higher waveform capture rate and to detect very fast signal transients that may be missed by DSOs.

Figure 3: Tektronix TDS3000C

Mixed signal oscilloscopes (MSO) (Figure 4) measure both digital and analog signals simultaneously. Obviously, they have more channels than traditional oscilloscopes, making them ideal for testing mixed-signal circuits.

By combining the analog channels of a scope with the logic channels of a logic analyzer, MSOs provide a comprehensive view of a system’s behavior. While it may not be practical to have a 16-channel oscilloscope, a 2 or 4 channel scope combined with a 16-channel logic analyzer function can provide the necessary capabilities to analyze even the most complex systems.

Figure 4: Tektronix 4 Series MSO

Digital sampling oscilloscopes (Figure 5) use a technique called equivalent-time sampling to measure signals. They are ideal for measuring repetitive signals that occur at high frequencies  up to 50 GHz or more, and have low duty cycles. They achieve this by collecting samples from several waveforms and assembling them to build a picture of the waveform.

To optimize for high frequency operation, these oscilloscopes have a different vertical amplifier topology. The signal is sampled prior to amplification to achieve maximum bandwidth. Then a lower frequency amplifier/attenuator combination can be used. However, this reduces the dynamic range of the instrument, limiting the maximum voltage that can be handled to around 3 volts peak to peak.

Figure 5: Keysight N1000A DCA-X

Theory of Operation

• An oscilloscope works by converting electrical signals into a visible waveform that can be analyzed. The signal is first fed into the oscilloscope, where it is amplified and displayed on a cathode ray tube (CRT) or digital display. The waveform displayed on the screen represents the amplitude of the signal over time.
• Waveform can be analyzed based on the amplitude, frequency, phase, and other characteristics. The amplitude of a waveform represents the voltage of the signal, while the frequency represents the number of cycles per second. The phase represents the relative timing of the waveform with respect to a reference signal.
• Signal acquisition involves the process of capturing and sampling the input signal. This can be done using a variety of techniques, such as direct probing, current probes, and voltage probes. The signal is then amplified and digitized for processing.
• Once the signal is acquired and digitized, it can be displayed and analyzed using a range of techniques. Oscilloscopes typically offer features such as triggering, cursors, measurements, and advanced analysis tools to aid in waveform analysis.

Choosing the right Oscilloscope

Choosing an oscilloscope can be a daunting task, with a wide range of specifications and features to consider. We suggest some steps which can help you find the right oscilloscope for your application.

Practical Uses of an Oscilloscope in Various Fields

First of all you need to know where you are going to use your oscilloscope and make a list of your use cases, try to think about the following criteria:

• Are you going to use it in one location or will you need light, easy to carry unit?
• How many input channels do you need? Standard is 2-4 channels that you can observe and compare signal timing, but for debugging a digital system you would likely need 8-16 channels.
• What record lengths do you need? A stable sine-wave signal only needs about 500 points and a basic oscilloscope will store around 2,000 points. But, to troubleshoot timing anomalies in a complex data stream, you might need a record length of up to 1 million points.
• Do you want to be able to connect the unit to a computer? Do you need networking, printing and file-sharing abilities?

Budget and Quality

Oscilloscopes vary in price, depending on the brand, model, features and specifications. You should first determine your budget, as this may vary depending on whether you want to purchase the oscilloscope for long-term or short-term use. Then you have to look for the available options in the specified price range. The opinion of other users and experts should also be taken into account in evaluating the reliability of the quality of the oscilloscope. Generally one should avoid unrealistically cheap low-quality oscilloscopes as those would likely yield inaccurate and many times confusing measurements.

Always review the manual and follow the safety precautions before using your oscilloscope.

Second-hand Oscilloscopes

Second-hand or pre-used oscilloscopes are available at over 90% discount over new ones. Also, the equipment that has already been discontinued by the manufacturers can be found as rental units.

As often times there is no way to test a used oscilloscope in person, there are a few details that can be checked to make sure everything is working as presented. The main detail to look for is in the picture of the instrument with an actual waveform shown on the screen – that means the oscilloscope really does work.
You can also zoom in and try to look through the front-panel settings and make sure matches the waveform shown on the screen.

Key Factors and 5X Rule

• Bandwidth

System bandwidth determines an oscilloscope’s fundamental ability to measure an analog signal – the maximum frequency range that it can accurately measure. So try to select an oscilloscope that has enough bandwidth to accurately capture the highest-frequency content of your signals. The 5X rule says that the bandwidth of the scope with the probe should be at least 5X the maximum signal bandwidth for better than +-2% measurement error. For example scopes with a maximum bandwidth of 100MHz can accurately capture the signals up to 20MHz.

• Sample Rate

The sample rate of an oscilloscope is similar to the frame rate of a movie camera. It determines how much waveform detail the scope can capture. Try to select an oscilloscope that has a maximum specified sample rate that’s fast enough to deliver its specified real-time bandwidth.

The 5X rule says to use a sample rate of at least 5X of your circuit’s highest frequency content, because the faster you sample, the less information you’ll lose. For example entry-level oscilloscopes have a sample-rate of 1-2 GS/s and mid-range have 5-10 GS/s.

• Number of Channels

When selecting a digital oscilloscope, you have to consider the number of channels of acquisition. While more channels are generally better for capturing multiple signals simultaneously, it’s also important to balance this with cost considerations. Ideally, you should choose a scope with enough channels to perform critical time-correlated measurements across multiple waveforms with ease. This ensures that you can accurately analyze complex signals and capture all relevant data for your application.

As mentioned above the standard oscilloscopes have 2-4 channels that you can view and compare signal timing, but for debugging a digital system you may need 8-16 channels.

• Memory Depth

Memory depth refers to the amount of data that the oscilloscope can store. It is typically specified in kpts or Mpts (kilopoints or megapoints) and determines the length of time that the oscilloscope can capture a signal.

Select an oscilloscope with a sufficient acquisition memory to capture your most complex signals with high resolution.

• Triggering

Triggering is used to start or stop data acquisition based on a specific event in the signal. Oscilloscopes offer a range of triggering options, including edge triggering, pulse width triggering, and video triggering. The triggering options of the oscilloscope should be suitable for the intended application. Edge triggering is the most basic triggering option, while more advanced triggering options, such as pulse width and video triggering, may be required for more complex applications.

Select an oscilloscope that offers advanced triggering for analyzing even the most complex waveforms. Better triggering options can help you detect challenging anomalies.

• Display Quality

A high-quality display can help you to accurately analyze your signals, especially for complex or fast-changing signals. Therefore, it’s recommended to select an oscilloscope that provides multiple levels of trace intensity gradation, allowing you to see subtle waveform details and signal anomalies.
This is due to the fact that intensity of a waveform can provide important information about how often a signal repeats. By detecting even subtle signal differences early on, you can avoid costly mistakes and improve your design process.

Conclusion

Oscilloscopes are essential tools for testing and debugging electronic systems, and there is a wide range of oscilloscopes available to suit different applications and budgets. When choosing your design partner, whether it is in house or outsourced,  it is important to consider how the new design will be validated and tested. 

Reach out to us to discuss how we use these tools during testing and validation phase to ensure the success of your next high speed digital design.

The post Using Oscilloscopes in High-Speed Digital Design appeared first on Tauro Technologies.

An Artificial Intelligence (AI) accelerator accelerates artificial intelligence applications such as artificial neural networks and machine learning. In the last decade, graphics processing units (GPUs) have seen increasing adoption for these applications since they efficiently perform image processing and mathematical neural network calculations. Fortunately for AI development, GPU manufacturers such as NVIDIA are making GPUs that greatly enhance AI performance, opening the door to many new computing products at the edge.  NVIDIA products have led the market with innovation and are widely used in AI computing. However, other specialty GPU providers offer enhanced performance on portions of AI computing, such as AI inferencing. 

What is a GPU?

A modern Graphical Processing Unit or GPU is similar to a CPU but makes use of parallel processing and is able to handle many processes and threads at the same time. Due to its parallel processing, a GPU is normally used for graphics processing and rendering.

GPUs have been around since the 1970s, primarily used for arcade games such as Sea Wolf and Space Invaders. Graphics cards were not commonly used in PCs until the mid-1980s, when the NEC μPD7220A became the first processor with a Large Scale Integration circuit chip, making it the most popular GPU. The next significant innovation was in the 1990s with S3 Graphics making the S3 86C911. This new GPU used 2D acceleration to gain a massive performance increase compared to its competitors. Today, a GPU is one of the most crucial hardware components of computer architecture.

Initially, the purpose of a video card was to take a stream of binary data from the central processor and render images to display. But modern graphics processing units are engaged in the most complex calculations, like big data research, machine learning, and AI.

While AI has existed since the 1990s in inference and training, AI accelerators did not enter the market until 10 years ago, when the workloads of AI processes became more intensive. Since 2010, AI accelerators such as field-programmable gate arrays (FGPA) and customized application-specific integrated circuits, (ASIC) are being replaced by commercial GPUs, which offer faster time to market and lower development costs. 

The GPU Market

Currently, the GPU industry is dominated by three large companies: NVIDIA, Intel, and AMD. These companies have been around for the longest, with NVIDIA pioneering the discrete GPU market since 2000 and putting them into a firm leadership position.  New entrants into the GPU market are picking a product niche and developing solutions that are efficient and designed to fill the appetite for higher performance with lower costs per watt of power. Up to 90% of the power consumed by an image processing application is accessing the RAM. Today, there are new entrants with differing approaches to building more efficient GPUs, including Mythic.AI, UntetherAI, Hailo, Blaize, etc., for edge AI computing.  These companies focus on avoiding data transfer between computing and memory to drive efficiency.  

GPU vs CPU

In the past, CPUs were used to process information for artificial intelligence. However, as GPUs have become more powerful over time, their ability to process more parallel information faster has made them a much better solution for AI. 

Integrating a GPU into an application:

GPUs are typically shipped as modules to be easily implemented into various applications. Chip-down GPU designs are intensive hardware and software projects; also, GPU vendors historically will only support Tier 1 customers and projects and encourage the rest of the applications to design a carrier that integrates their modules. 

Here are some common GPU module form factors:

PCIe

• This is the first and still most common form factor for GPU modules and is easily integrated with common PC motherboards with up to x16 Gen5 PCIe connections. However, the disadvantage is that they are large and bulky for many edge AI applications and typically require forced air to cool them.

MXM (Mobile Express Module)

• As the name indicates, the MXM form factor was developed to offer graphics processing module capabilities to smaller mobile computers such as laptops. It is also commonly used in edge SFF computing applications in markets such as military, medical, and transportation. The modules can be air cooled or conduction cooled.

M.2

• The M.2 standard replaces the mSATA standard and offers size and speed advantages for storage.  Gen4 PCIe x4 connections to the processor allow it to be also widely used for other computing functions, including GPS, LTE, IO, and smaller GPUs by vendors such as Hailo.  

E1.S EDSFF (Enterprise and Datacenter Small Form Factor)

• E1.S is the choice of next-generation storage modules.  It offers greater density and performance than the M.2 and other earlier form factors.

• Although it is being deployed in the datacenter server industry, it has not yet replaced M.2 as a standard in SFF Edge Computing.  
• Blaize is an example of a GPU being deployed in the ES.1 SFF, enabling up to 512 TOPS in a 1U server and 16-64 TOPS in an SFF computer.

SOM (System on Modules)

• System on Modules has been made popular for industrial edge computing by NVIDIA in products such as JETSON.
• Embedded ARM processors in the SOM enable a solutions provider to build a smaller, low-cost edge AI or graphics processing computer without needing a separate embedded CPU.

Chip-Down

• With many edge platforms, it is the most cost-effective to design a solution with a ‘chip-down’ GPU and a ‘chip-down’ CPU.  Tauro Technologies has designed these systems for several of the GPU vendors mentioned above.

GPU integration into a carrier board:

System design takes many factors into consideration, including cooling, power, I/O, storage, processing, etc., and each system requirement is different. Typically, GPU modules that are not chip-down are integrated into a main board or carrier board that has been customized to meet the application requirements.  

There are 2 main types of processors integrated into carrier boards:

• Intel x86: Due to the engineering complexity of Intel chip-down designs, many edge AI applications choose to use COMe or COM-HPC client-based modules to simplify their carrier design projects. Although the material cost of the module is higher than a chip-down solution, unless the product reaches modest volumes, it is more cost-effective to design with an x86-based module. 

• ARM-based processors: ARM processors are typically lower cost and take less power, making them ideal for many computer vision products when paired with a GPU.  Since there are few modules available based on open standards, most ARM-based products are custom designed with a chip-down processor such as NXP Cortex or Layerscape.  

Summary:

The advent of AI is opening the door for application-specific GPUs that are finely tuned to the objectives of the project. Tauro Technologies has broad experience implementing edge computers optimized for the application. If you wish to discuss a customized high-volume platform or a system which takes advantage of commercially available hardware and tools, reach out to us.

The post Use of GPUs in Edge AI Computing: appeared first on Tauro Technologies.

Serial communications protocols are vital to embedded systems.  While UART, I²C, and SPI have been used for short-distance device communication for decades, the benefits are not entirely apparent.

In order to connect peripherals to a computer, one of the following protocols is typically employed: a Universal Asynchronous Receiver Transmitter, (UART) Inter-Integrated Circuit, (I²C) or Serial Peripheral Interface (SPI). This blog will compare and contrast the features of each protocol and help you determine the best fit for your application.   

UART

Universal Asynchronous Receiver Transmitter (UART) is an asynchronous serial communication device with its roots dating back to the telegraph. There is no clock signal to synchronize or validate the data transmitted from the transmitter and received by the receiver (Asynchronous Serial Communication). It sends 1 bit at a time from least significant to most significant and uses start and stop bits to enable precise clocking. During packet transmission, UART uses what is called a parity bit, to enable checking if the information has changed during transmission. 

In addition, data transmission between devices can be in simplex, half-duplex, or full duplex modes.

Data is transmitted at baud rate measured in bits per second – some of the standard baud rates are 4800 bps, 9600 bps, 19200 bps, 115200 bps etc. Out of these, 9600 bps baud rate is the most commonly used.

UARTs must be set for the same bit speed, character length, parity, and stop bits for proper operation on the transmit and receive side. If the receiving UART detects mismatched settings a flag is sent in the host system memory to indicate a failure. 

The data in UART serial communication is organized into blocks called Packets or Frames. The structure of a typical UART data packet or the standard framing of the data is shown in the following table:

Advantages:

• Management is straightforward through hardware. It is utilized by standard protocols including RS-232/485/422.
• Long-distance up to 1km for RS-422/485 buses.
• Requires only two wires for full-duplex data transmission (other than power lines).
• Parity bit ensures basic error checking is integrated into the data packet frame.
• No need for clock or any other timing signal.

Disadvantages:

• Communication is only between two devices where the baud rate, data bit count, parity bit, and stop bit count need to be identical.
• Typically the size of the data frame is limited to only 9 bits (8 data bits, no parity bit and one stop bit).
• Overrun errors if the buffer space is insufficient.
• Size of data in the frame is limited.

I²C

Unlike UART, an Inter-Integrated Circuit is a synchronous serial communication interface and utilizes the system clock. It means that data bits are transferred one by one at regular intervals of time set by a SCL clock line. It is used primarily for short distance, intra-board communication between low speed controllers and processors and is ideal for applications that link up to many components on a bus. Although I²C is typically implemented with a single master and multiple slaves on the bus, it can also be implemented with multiple masters.  Each slave device has a unique address and I²C enables the master to send and request data from a particular slave device utilizing a start bit to the slave address.  

I2C only uses two wires to transmit data between devices:

• SDA (Serial Data) – The line for the master and slave to send and receive data.
• SCL (Serial Clock) – The line that carries the clock signal (common clock signal between multiple masters and multiple slaves).

The structure of a typical I²C Data Packet or the standard framing of the data is shown in the following table (Note: The bold signals are sent by slave and the other signals by master):

Advantages:

• Addressing function enables multiple masters and slaves.
• Control a network of devices with only 2 I/O pins.
• Simple mechanism for validation of data transfer.
• I²C networks are easy to scale. New devices can simply be connected to the two common I²C bus lines.
• No need for prior agreement on data transfer rate as in UART communication.

Disadvantages:

• Slower speed (up to 100 kbit/s in standard mode, 400 kbit/s in fast mode)
• Half-duplex interface.
• Only one slave can be addressed at a time.

SPI

The Serial Peripheral Interface (SPI) is also a synchronous serial communication device which is used primarily for short distance communication. The main difference between SPI and I²C is that SPI uses a full-duplex communication with master-slave topology. Similar to I²C , SPI can be used to access multiple slave devices.

At the beginning of communication, the bus master configures the clock (typically 50 MHz) and sends data to the slave.  During a single SPI clock cycle, a full duplex of data transmission is completed.  Unlike UART, there are no start and stop bits – this enables continuous data transmission and the communication achieves higher speeds than I²C and UART.

The maximum data rate limit is not specified in the SPI interface. Standard data rates include 10 Mbps transfer rate with some devices reaching 100Mbps transfer rate.

The SPI bus consists of 4 signals below:

• Master – Out / Slave – In (MOSI)
• Master – In / Slave – Out (MISO)
• Serial Clock (SCLK)
• Chip Select (CS) or Slave Select (SS)

Depending on the values of Clock Polarity (CPOL) and Clock Phase (CPHA), there are 4 modes of operation of SPI:

• Mode 0 is active when Clock Polarity is LOW and Clock Phase is LOW (CPOL = 0 and CPHA = 0). Data sampled on rising edge and shifted out on the falling edge.
• Mode 1 is active when Clock Polarity is LOW and Clock Phase is HIGH (CPOL = 0 and CPHA = 1). Data sampled on the falling edge and shifted out on the rising edge.
• Mode 2 is active when Clock Polarity is HIGH and Clock Phase is LOW (CPOL = 1 and CPHA = 0). Data sampled on the falling edge and shifted out on the rising edge.
• Mode 3 is active when Clock Polarity is HIGH and Clock Phase is HIGH (CPOL = 1 and CPHA = 1). Data sampled on the falling edge and shifted out on the rising edge.

The structure of a typical SPI data packet or the standard framing of the data is shown in the following image:

Advantages:

• Full-duplex is default for the SPI protocol.
• Slaves do not require a unique address.
• Not limited to 8-bit word size.
• Real-estate savings on embedded boards.
• High data transfer speed.
• No need for individual addresses for slaves as CS or SS chip-select lines are used.
• Only one master device is supported, removing the possibility of conflicts.
• SPI uses less power than I²C.

Disadvantages:

• No protocol-level error checking function and no hardware slave acknowledgement.
• Short distances (up to 10m).
• Each additional slave requires an additional dedicated pin on the master for CS or SS.
• There is no acknowledgement mechanism and hence there is no confirmation of data receipt.
• Slowest device determines transfer speed.

Summary

In general, you can use UART if you are looking for a simple connection between 2 devices, I²C if you are connecting several devices on the same bus, and SPI becomes the ideal choice if you require a faster interface.  Whether you need UART’s tried and true operation, or want to utilize the expansion offered by I²C or the high speed of SPI, Tauro Technologies can implement a system using the most appropriate interface for your project.  

Interested to know more? Get in touch with us for details

The post Serial Protocols & Their Uses: I2C, UART, SPI appeared first on Tauro Technologies.

For quite a while, since the rise of smartphones in the late 2000s, the computer processors market has been dominated by ARM central processing units (CPUs) based on the reduced instruction set computer (RISC) architecture. Recently, however, a strong competitor has emerged with a considerably different approach towards the CPU architecture in microprocessors, mobile systems and microcontrollers. The name of this potential ARM killer is RISC-V (pronounced as “risk-five”). 

Over the last couple years, the debate regarding the competition between ARM and RISC-V has been getting more and more vibrant. 

Will RISC-V ultimately replace ARM as the top CPU specification or will both technologies coexist? Let’s take a closer look at these two computer processor architectures, their technical specifications and how they are different from each other. 

What is ARM? 

ARM (originally known as Acorn RISC Machine, ARM stands for Advanced RISC Machines) is a family of RISC instruction set architectures for computer processors, available for various computing devices and environments. 

The ARM CPU architecture is developed by the Arm Ltd company, which licenses the architectures to other companies, allowing them to design their own products that incorporate different components, including interfaces and memory. 

There have been a number of generations of ARM architecture. The original version, ARM1, was introduced in 1985, almost 40 years ago. First application for ARM processors was as an additional second processor for the BBC Micro, providing support to speed up the simulation software. ARM1 used 32-bit internal structure but also had 26-bit address space, limiting it to 64 MB of main memory. This limitation was removed in ARM 3.

ARM 8-A, released in 2011, received the support for 64-bit address space and 64-bit arithmetic. 

ARM processors quickly gained popularity due to their low power consumption, lower costs compared to available alternatives, and minimal heat generation. 

Even though ARM CPUs were widely used since the initial release of this architecture, they really came to power in the late 2000s, upon the release of the first smartphones. Being the best CPU choice for portable devices due to light weight and low power consumption, ARM processors are preferred by the manufacturers of smartphones, tablets and laptops. For the same reasons, ARMs are also widely used in embedded systems. 

According to the official data, more than 200 bln ARM chips have been produced around the world as of 2021. 

What is RISC? 

Since we already mentioned the RISC a number of times, a few words about it need to be said as well. 

RISC is a technology designed to simplify the individual instructions provided to the computer to perform certain tasks. The difference between RISC and CISC (a complex instruction set computer) is that RISC architecture typically requires more instructions provided to a computer in order to complete tasks as individual instructions in RISC are written in simpler code. 

One of the key concepts of RISC computers is that every instruction performs only one function during single CPU cycle. 

What is RISC-V?

RISC-V is basically the fifth generation of the RISC architecture, provided as an open standard instruction set architecture (ISA) based on the RISC standard principles. Unlike the majority of other ISA designs, it is provided under the open source license, so it’s free to use for all the computer chip producers.

The RISC-V specification defines both 32-bit and 64-bit address space options, and additionally includes a description of a 128-bit flat address space variant. 

The RISC-V is a load–store architecture, using IEEE 754 floating-point instructions. RISC-V ISA also includes instruction bit field locations as a way to simplify the use of multiplexers in CPUs. 

Started with a goal to create a practical open source ISA that will be easily deployable in various hardware and software designs, including embedded systems, the RISC-V ISA is a continuation of a long history of CPUs architecture design projects developed at the University of California, Berkeley, since the late 1980s.

History of the RISC-V specification development

The project to develop RISC-V specification was originally started in 2010 by the University of California experts with an intent to create a practicable instruction set that will be available for practical use in various CPUs manufacturing. 

Dr. Krste Asanović, a professor of computer science at UC Berkeley, was an author of the project to develop RISC-V. Eventually, Dr David Patterson, another UC Berkeley professor and one of the creators of the original RISC chips back in the early 1990s, joined the project.

As any ISA needs to be stable for commercial use, the RISC-V Foundation was formed in 2015 with a goal to develop, maintain and publish the intellectual property related to the RISC-V specification. The original authors of the project at UC Berkeley have transferred all the rights to this non-profit corporation controlled by its members.

Currently, the RISC-V Foundation comprises over 325 members, including representatives from companies such as Google, NVIDIA, Microsemi, Western Digital. The RISC-V Foundation members participate in the development of the RISC-V ISA specification and related projects. 

In 2019, due to the U.S. trade regulations concerns as the main reason, the RISC-V Foundation relocated to Switzerland. In 2020, the organization was renamed as RISC-V International, becoming a Switzerland-registered nonprofit business association.

Today, the RISC-V International publishes all the documentation and specifications related to RISC-V designs, which remains open source and available for everyone to use free of charge. However, only the members of RISC-V International can vote to approve any changes to RISC-V specifications. 

ARM vs RISC-V Comparison 

Here’s a table comparing technical specifications of ARM and RISC-V. 

Final thoughts. ARM vs RISC-V: Which one to choose? 

As you can probably tell from the comparison chart above, there is no simple answer to this question. 

In many ways, right now, ARM-based CPUs are still a better option, mainly due to much longer lifecycle and the fact that ARM Ltd has invested billions of dollars into this specification over the years. ARM processors have a huge market share, being used in the majority of smartphones, as well as laptops and even PCs that are choosing ARM instead of x86 architecture-based designs. 

We could say, however, that RISC-Vs are the future and a very strong contender to the throne of the most used computer processors architecture. RISC-V can provide better performance using a minimum amount of power. The fact that RISC-V is open source and free to use by any processor manufacturers is also a huge advantage.

Some manufacturers, such as Western Digital, for example, have already started implementing the RISC-Vs in their microcontrollers attached to RAMs and SSDs. 

RISC-V is also getting increasingly popular in IoT devices and embedded systems of various kinds, due to its highly scalable nature. But it will undoubtedly take several years for industry players to transition to using RISC-V instead of ARM-based designs. 

The Tauro Technologies’ team of electronic engineers and designers has a proven track record of successfully designing custom hardware for various kinds of products in multiple technology fields. Drawing on the specific needs of our clients, we select and apply various engineering methods to electronic product development and manufacturing in order to achieve the desired result. Utilizing our in-house PCB assembly and debug expertise, we are able to build and evaluate your prototypes before high-volume manufacturing, rapidly and cost-efficiently. 

Interested to know more? Get in touch with us for details.

The post RISC-V vs ARM. Which One To Choose? appeared first on Tauro Technologies.

Today we would like to talk about I2C protocol, issues related to I2C bus conflicts and ways to address those issues. So, without further ado, let’s get to it. 

What is I2C? 

I2C stands for inter-integrated circuit also known as I2C or IIC. It is one of the most popular bus interfaces used for attaching various peripherals to a controller/CPU.

I2C is a synchronous, multi-controller and multi-target bus interface. Originally invented by Philips Semiconductors (currently NXP Semiconductors) in 1982, today I2C is widely used as a protocol for short-distance, intra-board communication of serial devices with each other. 

Today I2C is the communication protocol of choice for various ICs manufactured by more than 50 companies. Some of the largest manufacturers of compatible I2C products are Siemens, Texas Instruments, STMicroelectronics, Motorola, NEC, Nordic Semiconductor and Intersil.

I2C uses only two bidirectional open-drain lines: serial data line (SDA) and serial clock line (SCL) for synchronous data communication. I2C protocol was originally designed to use 7-bit addressing and enable 100 Kbps communication between the chips on a printed circuit board (PCB). Over the years, however, I2C was updated for 10-bit addressing and faster data transmission, and today provides speeds up to 3.4 Mbit.

Being able to support multiple ICs on a single serial communication bus makes I2C perfect for a wide variety of applications in both consumer and industrial electronics. 

I2C buses are used in a wide range of control architectures, including System Management Bus (SMBus), Advanced Telecom Computing Architecture (ATCA), Display Data Channel (DDC), Power Management Bus (PMBus), Intelligent Platform Management Interface (IPMI) and others. SMBus specifically is considered to be a subset of I2C that defines stricter usage of the protocol for better interoperability and higher speed. 

Common I2C Applications

As we already mentioned above, due to the simplicity of implementation and its low cost, I2C protocol is widely used in modern-day electronic devices. Here are some of the most common applications for I2C communication protocol today: 

• Communicating with different microcontrollers, 

• Accessing DACs (digital-to-analog converters) and ADCs (analog-to-digital converters),

• Reading memory ICs,

• Reading hardware sensors,

• Connecting EEPROMs, I/O interfaces, and other parts of an embedded system,

• High-speed communication with a large number of peripheral devices, 

• Directing and transmitting user-directed actions.

When it comes to specific devices using I2C, you can commonly find this protocol in various sensors (temperature, electrical voltage, etc.), real-time clock (RTC) chips, fan controllers, electric power supply solutions and many other types of control and measurement electronic devices. 

Here are some examples of devices that use I2C protocol as a communication interface: 

• Accelerometers
• Color sensors
• Gyroscopes
• Temperature sensors
• Humidity sensors
• Pressure sensors
• Analog-to-digital converters
• Authentication devices
• Power management ICs
• Magnetometers (compasses)
• Touch sensors
• Digital audio signal processors,
• LCD controllers and drivers,
• Decoder for satellite and cable TV

I2C Bus Conflicts

Being such a widely used protocol, I2C certainly has its fair share of issues and common problems. 

As the I2C compatible modules and chips use7-bit addresses, one I2C bus can simultaneously support up to 127 devices on the same bus. Some of the addresses are so-called ‘general call addresses’ used to send messages to all devices on the bus. Also, every device on the I2C busmust have a unique address for correct master/slave communication. 

One very common I2C issue occurs when putting multiple devices that share the same address on an I2C bus. When a large number of sensors and peripheral devices are connected to a single bus, it is possible that some devices will use the same address which would result in a conflict. This happens, for example, when connecting multiple SFP (small form-factor pluggable) connectors to a single I2C bus. As a result, the EEPROM device embedded in SFP transceiver will end up sharing the same 7-bit address with the other SFP transceivers on the bus. 

Here are three common ways to address this problem that we would like to talk about in this article. 

• Shared data line with dedicated clock lines for each device

If you have a microcontroller that can have multiple functions on the GPIO lines, one way to address this problem would be to share the data line across multiple I2C devices that have the same address, and then use a dedicated clock line to select every single device at a time. 

In this case you are sharing the data line but and using individual clocks that requires reconfiguring the CPU pins, and can hardly be considered as an optimal solution. Also, this method is a bit sophisticated as it requires special support on the processor’s side to be able to reconfigure the pins. On the other hand, this is also the most cost-effective way as it does not require additional components. 

• I2C MUX

Second, more generic approach to this problem is to use an I2C MUX, a multiplexing circuit able to connect slave devices with the same address to different communication buses, interchanging communication channels by programming the MUX. 

With this method, one can simply spread the conflicting devices across the bus by using I2C MUX. It is also safe to say that using I2C MUX is the most straightforward and easy to implement solution to this problem. 

• I2C Address Translator

The third way is to use an I2C Address Translator, a component designed to bridge two segments of an I2C bus, adding an offset to incoming addresses on the master side and retransmitting the updated address to the slave side. Using I2C Address Translator, allows replacing the hardwired address of one or more I2C slave devices with a different address. 

This method also allows slave devices with the same hardwired address to operate on the same I2C bus. Using an I2C Address Translator may be considered a slightly inconvenient approach compared to the other two as it still leaves space for potential address conflicts within an I2C bus. 

Final thoughts 

It is extremely important to make sure that there are no I2C address conflicts on the bus. Having an I2C bus with an address conflict (they are often quite difficult to detect) can cause major problems and result in undefined behavior on the bus. 

So it is highly advisable to take measures and make sure there are no I2C address conflicts within your system. The ideal solution is to put conflicting devices on different I2C buses, but this option is not always available which is why the ultimate goal should be achieving no I2C address conflicts by utilizing the least number of components. 

The Tauro Technologies’ team of electronic engineers and designers has a proven track record of successfully designing custom hardware using I2C bus for various kinds of products. Drawing on the specific needs of our clients, we select and apply various engineering methods to electronic product development and manufacturing in order to achieve the desired result. Utilizing our in-house PCB assembly and debug expertise, we are able to build and evaluate your prototypes before high-volume manufacturing, rapidly and cost-efficiently. 

Interested to know more? Get in touch with us for details.

The post I2C Protocol – Solving I2C Address Conflicts appeared first on Tauro Technologies.